Kayhan Kucukcakar

Exploiting Setup–Hold-Time Interdependence in Static Timing Analysis

A methodology is proposed to exploit the interdependence between setup- and hold-time constraints in static timing analysis (STA). The methodology consists of two phases. The first phase includes the interdependent characterization of sequential cells, resulting in multiple constraint pairs. The second phase includes an efficient algorithm that exploits these multiple pairs in STA. The methodology improves accuracy by removing optimism and reducing unnecessary pessimism. Furthermore, the tradeoff between setup and hold times is exploited to significantly reduce timing violations in STA. These benefits are validated using industrial circuits and tools, exhibiting up to 53% reduction in the number of constraint violations as well as up to 48% reduction in the worst negative slack, which corresponds to a 15% decrease in the clock period

Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times

A methodology is proposed for interdependent setup time and hold time characterization of sequential circuits. Integrating the methodology into an industrial sign-off static timing analysis tool is described. The proposed methodology prevents optimism and reduces unnecessary pessimism, both of which exist due to independent characterization. Furthermore, the tradeoff between interdependent setup and hold times is exploited to significantly reduce slack violations. These benefits are validated using industrial circuits and tools

Designing and Validating Process-Variation-Aware Cell Libraries

Modeling process variations in cell libraries is fundamental to enabling statistical static timing analysis. Achieving it in an industrial setting has many stringent requirements. A generic model is proposed that satisfies these requirements. The results of its rigorous validation are explained