Filip Bauwens

An industrial process for 650V rated GaN-on-Si power devices using in-situ SiN as a gate dielectric

This paper reports on an industrial DHEMT process for 650V rated GaN-on-Si power devices. The MISHEMT transistors use an in-situ MOCVD grown SiN as surface passivation and gate dielectric. Excellent off-state leakage, on-state conduction and low device capacitance and dynamic Ron is obtained. Initial assessment of the intrinsic reliability data on the in-situ SiN is provided.

XtreMOS : The First Integrated Power Transistor Breaking the Silicon Limit

Record performance of a novel power transistor integrated in a 0.35 μm power IC technology is reported. Measured specific on-state resistance of 33 mOhm*mm2 for a 94 V breakdown is breaking the silicon-limit and is the lowest reported value to date. The device outperforms its nearest rival by a factor of 2.5. The device consists of the stacking of a vertical MOS on a fully depleted vertical drift layer, leading to a high cell density

Electron trapping and interface trap generation in drain extended PMOS transistors

The hot carrier behavior of a p-type lateral drain extended MOS (DeMOS) is for the first time investigated using charge pumping (CP). In an early stage of hot carrier stress, electron injection and trapping occurs. With increasing stress time, the interface trap formation in the spacer oxide becomes the dominant mechanism. In this way, the abnormal degradation of the specific on-resistance Ron is explained.

Charge trapping effects and interface state generation in a 40 V lateral resurf pDMOS transistor

This paper investigates the degradation of a lateral resurf 40V pDMOS transistor under hot carrier stress using variable base charge pumping experiments. Upon stressing, the device exhibits N/sub it/ formation in the gate overlapped drift region and electron trapping in the drift region birds beak. Injection of electrons occurs at a spot approximately 50 nm from the birds beak tip. The degradation of the electrical parameters upon hot carrier stress is only correlated with the amount of injected electrons, and not with the N/sub it/ formation. The trapped electron charge will cause a walk-in of the off-state V/sub bd/.

Analytical Switching Loss Model for Superjunction MOSFET With Capacitive Nonlinearities and Displacement Currents for DC–DC Power Converters

A new analytical model is presented in this study to predict power losses and waveforms of high-voltage silicon superjunction MOSFET during hard-switching operation. This model depends on datasheet parameters of the semiconductors, as well as the parasitics obtained from the printed circuit board characterization. It is important to note that it also includes original features accounting for strong capacitive nonlinearities and displacement currents. Moreover, these features demand unusual extraction of electrical characteristics from regular datasheets. A detailed analysis on how to obtain this electrical characteristic is included in this study. Finally, the high accuracy of the model is validated with experimental measurements in a double-pulse buck converter setup by using commercial SJ MOSFET, as well as advanced device prototypes under development.

Internal self-damping optimization in trench power FETs for high-frequency conversion

The impact of the shield resistance (Rsh) on the waveform ringing and system efficiency is assessed in this work for 30V trench power FETs with shielded-gate (TP-FETs). Two different approaches, named distributed and local Rsh, are extensively investigated by experimental and numerical simulation tools. A layout distributed Rsh emerges as the ultimate solution to maximize the self-damping without penalization on the switching power losses or the product cost. The practical implementation of a TP-FET with distributed Rsh in a 12V-to-1.2V buck converter results in one of the best tradeoffs ever reported between overvoltage (<;3.5V) and peak efficiency (~88%) when operating at 1.3MHz.

Body-diode related losses in Shield-Plate FETs for SiP 12V-input DC/DC buck converters operating at high-frequency (4MHz)

The power losses in System-in-Package (SiP) 12V-input DC/DC buck converters with advanced 30V Shield-Plate FETs (SP-FETs) are assessed by experiment and simulation with special interest in the body-diode contribution. Unlike previous work, rise/fall times and on/off deadtimes are in the nanosecond range to provide high efficiency at high frequency operation (1-4MHz).

Reliability assessment of deep trench isolation structures

An extensive investigation of the reliability of deep trench isolation structures upon reverse bias stress is performed. By using the variable base level charge pumping technique, it is shown that the degradation of the trench primarily originates from N/sub it/ formation at the inner trench corners. The reliability is improved by introducing cut corners.

A high-speed silicon FET for efficient DC-DC power conversion

A novel silicon device architecture for DC-DC power conversion is reported. Efficient switching at high frequencies (1-5 MHz) is achieved by simultaneously reducing gate charge, reverse capacitance, and gate resistance while still maintaining good on-state resistance and off-state breakdown voltage. Power efficiencies in excess of 88% were realized in a synchronous buck converter running at 1.3 MHz.

Thermal resistance assessment in multi-trenched power devices

Abstract For the first time the thermal resistance ( R th ) of Multi-Trenched (MT) power devices is evaluated and compared with their Deep Trench Isolation flanked (DTI-flanked) and bulk counterparts. The R th extraction is carried out by adapted test structures based on the four-point heater/sensor method. Additional TCAD simulation supports the experimental stationary values and proves that dynamic heating can limit the MT power devices energy capability.