Filip Christiaens

Thermomechanical models for leadless solder interconnections in flip chip assemblies

Analytical thermomechanical models have been developed in order to calculate the thermally induced stresses in leadless solder interconnection systems. Two different analytical models are highlighted: the peripheral and area array thermomechanical model which describe the thermally induced stresses for two components connected to each other with a peripheral, respectively, area array of joints. The analytical models are based on structural mechanics and have the ability to characterize the nature and estimate the magnitude of the joint stresses. Using these models, structural design optimization of interconnection systems can be performed very quickly in order to reduce time consuming experiments and finite element simulations. It is found that the largest stresses in the solder joints of flip chip assemblies are at the top and bottom surface of the connection and that they are especially caused by bending moments subjected to the joints. Comparisons with finite element simulations have proved a good accuracy of the thermomechanical models.

Modified micro-macro thermo-mechanical modelling of ceramic ball grid array packages

Abstract The ceramic ball grid array (CBGA) packages are typically used for high I/O count area array assemblies. As the package size is large, the distance to neutral point is also high resulting in a large thermal deformation mismatch between the CBGA package and the printed circuit board (PCB). In order to cope with this problem, a special solder joint connection is used. As CBGA assemblies are used for high pin count assemblies, a full 3D thermo-mechanical modelling of an assembly to an FR4 board is not possible anymore. Therefore, a modified micro–macro methodology is proposed where only the critical solder joint is modelled in detail, while the other connections are replaced by equivalent connections. For several CBGA configurations, simulation results are correlated to thermal cycling test results. Finally, a parameter sensitivity study shows that the PCB properties have a significant influence on the solder joint reliability.

Experimental Thermal Characterisation of Electronic Packages in a Fluid Bath Environment

This paper focuses on the application of a fluid bath system for experimental thermal characterisation of electronic packages. Problems related to the standard method for Rjc and Rja measurements in a fluid bath environment are addressed. In order to overcome these problems and to increase the accuracy and repeatability of Rjc fluid bath measurements, a submerged liquid jet impingement cooling scheme is proposed. Using impinging liquid jets, a quasi isothermal boundary condition over the package surfaces can be obtained, minimising the external convective temperature difference. As a result, Rjc approximates Rjc, which can be measured without system disturbance effects. The advantages of this new experimental boundary condition for thermal characterisation of electronic packages will be illustrated with practical thermal resistance measurements on a Plastic Quad Flat Package (PQFP) and a Ceramic Pin Grid Array (CPGA).

Design of an optimal heat-sink geometry for forced convection air cooling of Multi-Chip Modules

An assessment is made of the limits to the cooling capability of forced convection air cooling of multi-chip modules. Therefore heat-sinks of different geometries are analysed, using a new design criterion which involves both the effects of heat transfer performance and pressure drop. It is shown that, when pressure drop is taken into account, plate fin heat-sinks have a better cooling performance than offset-strip fin or pin fin heat-sinks. The dimensions of a plate-fin heat-sink are optimized using an analytical model. The optimal plate-fin heat-sink has a cooling performance comparable to what is normally achieved by integral water cooling. To confirm the thermal performance of the optimal plate fin heat-sink, measurements are carried out in a low speed windtunnel.

Modelling of thermal vias in thin film multichip modules

A semi-analytical model is presented for evaluating the thermal resistance of via networks used in thin film multichip modules. Correlations between dimensionless groups were derived from numerical data. Therefore, the via network was divided in three basic elements. This allows one to reconstruct the network as a series and parallel connection. The results of this semi-analytical model are compared with those of an existing analytical model and a 3D finite element model. Good agreement between the three models was obtained. The heat conduction efficiency of a staggered thermal via network is defined and the influence of several parameters was investigated.<<ETX>>

Thermal and Thermo-Mechanical Evaluation of a ‘Chip in Moulded Interconnect Device’

In this paper, a thermal and thermo-mechanical evaluation study of a new packaging approach, called CIMID (Chip in Moulded Interconnect Device), will be presented. The thermal performance of a prototype CIMID structure has been investigated by means of finite element analysis and experimental thermal characterisation techniques. Thermally induced stresses were calculated for a uniform cooling condition, which simulated the cooling down process after the encapsulation and curing process. The thermo-mechanical behaviour of the CIMID assembly was compared to those of a chip on PCB assembly.