Eric Beyne

Thermal modeling and management in ultrathin chip stack technology

This paper presents a thermal modeling for power management of a new three-dimensional (3-D) thinned dies stacking process. Besides the high concentration of power dissipating sources, which is the direct consequence of the very interesting integration efficiency increase, this new ultra-compact packaging technology can suffer of the poor thermal conductivity (about 700 times smaller than silicon one) of the benzocyclobutene (BCB) used as both adhesive and planarization layers in each level of the stack. Thermal simulation was conducted using three-dimensional (3-D) FEM tool to analyze the specific behaviors in such stacked structure and to optimize the design rules. This study first describes the heat transfer limitation through the vertical path by examining particularly the case of the high dissipating sources under small area. First results of characterization in transient regime by means of dedicated test device mounted in single level structure are presented. For the design optimization, the thermal draining capabilities of a copper grid or full copper plate embedded in the intermediate layer of stacked structure are evaluated as a function of the technological parameters and the physical properties. It is shown an interest for the transverse heat extraction under the buffer devices dissipating most the power and generally localized in the peripheral zone, and for the temperature uniformization, by heat spreading mechanism, in the localized regions where the attachment of the thin die is altered. Finally, all conclusions of this analysis are used for the quantitative projections of the thermal performance of a first demonstrator based on a three-levels stacking structure for space application.

Ultra thin electronics for space applications

Higher performance, increasing I/O requirements and smaller chip size are putting more demands on technology for increased density. If most of the demand is coming from consumer electronics for next generation of Internet portable devices, similar trends are seen in the space industry with the future generation of broadband multimedia satellite payloads. A new patented packaging technology for highly complex digital application is presented in this paper. 3D interconnect of ultra-thin silicon die (15 /spl mu/m thick) is enabled through slightly modified MCM-D technology. Collective fabrication is done with specifications which could respond to space environment standards. We review the key enabling technologies used to fabricate an ultra compact channelizer composed of 3 cascaded, 496 I/O ASICs. The 3D module has a footprint of 25/spl times/25 mm/sup 2/ with overall thickness of 500 /spl mu/m which makes it compatible of any chip scale package that will allow thermal management for 7.8 W power dissipation.

Residual thermomechanical stresses in thinned-chip assemblies

A new technology for the three-dimensional (3-D) stacking of very thin chips on a substrate is currently under development within the ultrathin chip stacking (UTCS) Esprit Project 24910. In this work, we present the first-level UTCS structure and the analysis of the thermomechanical stresses produced by the manufacturing process. Chips are thinned up to 10 or 15 /spl mu/m. We discuss potentially critical points at the edges of the chips, the suppression of delamination problems of the peripheral dielectric matrix and produce a comparative study of several technological choices for the design of metallic interconnect structures. The purpose of these calculations is to give inputs for the definition of design rules for this technology. We have therefore undertaken a programme that analyzes the influence of sundry design parameters and alternative development options. Numerical analyses are based on the finite element method.