Filip Tavernier

High-Speed Optical Receivers With Integrated Photodiode in 130 nm CMOS

The design and measurement of two optical receivers with integrated photodiode in 130 nm CMOS is presented. The low bandwidth, which is typical for photodiodes in CMOS technologies, is circumvented by a differential photodiode topology on the one hand and by including an optimized equalizer in the receiver chain on the other hand. The low responsivity of a CMOS photodiode is compensated by a very low-noise design for the differential TIA. The disadvantage of such a low-noise design is its high power consumption. Therefore, a design strategy is presented where part of the circuit is biased in weak inversion. Doing so, the power consumption is decreased from 138 mW for the standard design to only 74.16 mW. Both designs are measured optically with 850 nm modulated light and are able to operate at 4.5 Gbit/s with a BER lower than 10-12. The sensitivities for this BER and speed are - 3.8 dBm and -3.4 dBm respectively. The receivers even work up to 5 Gbit/s for BER values around 10-9.

Power efficient 4.5Gbit/s optical receiver in 130nm CMOS with integrated photodiode

An optical receiver with integrated photodiode in 130 nm CMOS is presented. The extremely unfavourable optical and electrical performance of a differential photodiode in this technology, namely a very low responsivity of only 5 mA/W, an optical bandwidth of 500 MHz and a large photodiode capacitance of 1pF, have been solved so that bitrates of 4.5Gbit/s and higher can be received for BER values as low as 10-12. The power consumption for this is only 74.16 mW due to a biasing in weak inversion.

High-speed optical receivers with integrated photodiode in nanoscale CMOS

Introduction.- Optical communication - A high-level perspective.- From light to electrical current - The photodiode.- From current to voltage - The transimpedance amplifier.- Increasing the speed - The equalizer.- Towards a rail-to-rail voltage - The post amplifier.- Chip implementations.- Conclusions.

A Gigabit Optical Receiver with Monolithically Integrated Photodiode in 0.18 μm CMOS

An optical receiver with monolithically integrated photodiode in a standard 0.18 mum CMOS technology is presented. At 1.2 Gbit/s, the optical sensitivity is -8 dBm for a BER of 10-12, while the off-chip output amplitude is 500 mVpp into a 50 Omega load. The post-amplifier can handle bitrates up to 5 Gbit/s with a BER of 10 -12 and a dynamic range larger than 41 dB. Current consumption of the complete receiver is 250 mA from a 1.8 V power supply. 210 mA of the total current is dissipated in the post-amplifier and output buffer.

A 5.5 Gbit/s optical receiver in 130 nm CMOS with speed-enhanced integrated photodiode

The design and measurement of a high-speed optical receiver is presented. The intrisically low speed of a silicon photodiode is increased by a new photodiode structure which combines a high speed and a high responsivity. On top of this, an equalizer is used to increase the attainable bit rate even more. The receiver, existing from a photodiode, TIA, equalizer and post amplifier is integrated in a standard 130 nm CMOS technology. At a bit rate of 5.5 Gbit/s and an optical input power of −3.4 dBm, the BER is below 10−12. The power consumption is only 58.5 mW.

A high-speed POF receiver with 1 mm integrated photodiode in 180 nm CMOS

The design and measurement of an optical receiver is presented. To minimize cost, it is completely integrated on silicon in a CMOS process. In spite of the large parasitic photodiode capacitance, transient measurements are shown up to 800 Mbit/s.

When hardware is free, power is expensive! Is integrated power management the solution?

In the last several years, significant efforts and advances have been made towards the CMOS integration of power converters. In this paper, an overview is given of what might be considered the next step in this domain: AC-DC conversion, efficient high-ratio voltage conversion, wide operating range and energy storage for energy scavenging. The main focus is on CMOS integration as this is the ultimate goal from any system integration point of view. Also, an overview of the state of the art will be discussed.

A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS

A PLL (ePLL) is presented that is intended to be used as a frequency multiplier. The ePLL accepts 40, 80, 160 or 320MHz as a reference and generates clocks at the same frequencies, regardless of the input clock. Moreover, the outputs are available with a phase resolution of 90° for the 40, 80 and 160MHz output and 22.5° for the 320MHz output. The radiation-hard design, integrated in a 130nm CMOS technology, is able to operate at a supply voltage between 1.2V and 1.5V.

A low power, area efficient limiting amplifier in 90nm CMOS

A low power limiting amplifier with area efficient offset compensation in 90nm CMOS is presented. The large time constant needed in the offset compensation feedback loop is boosted by an inverting amplifier to reduce the chip area. On top of this, to reduce the chip area even more, negative capacitors are applied to increase the bandwidth instead of making use of the inductive peaking technique. The proposed circuit has a small-signal gain of 35dB and a bandwidth of 4.15GHz. The input sensitivity for a BER of 10−12 is 2.75mV, 2.9mV and 3.75mV for a bitrate of 3, 4 and 5Gbit/s respectively. The power consumption is only 14.7mW and the area of the circuit is 0.12mm2.

A 10 Gb/s laser driver in 130 nm CMOS technology for high energy physics applications

The GigaBit Laser Driver (GBLD) is a key on-detector component of the GigaBit Transceiver (GBT) system at the transmitter side. As part of the design efforts towards the upgrade of the electrical components of the LHC experiments, a 10 Gb/s GBLD (GBLD10) has been developed in a 130 nm CMOS technology. The GBLD10 is based on the distributed-amplifier (DA) architecture and achieves data rates up to 10 Gb/s. It is capable of driving VCSELs with modulation currents up to 12 mA. Moreover, a pre-emphasis function has been included in the proposed laser driver in order to compensate for the capacitive load and channel losses.