Carolien Hermans

A Gigabit Optical Receiver with Monolithically Integrated Photodiode in 0.18 μm CMOS

An optical receiver with monolithically integrated photodiode in a standard 0.18 mum CMOS technology is presented. At 1.2 Gbit/s, the optical sensitivity is -8 dBm for a BER of 10-12, while the off-chip output amplitude is 500 mVpp into a 50 Omega load. The post-amplifier can handle bitrates up to 5 Gbit/s with a BER of 10 -12 and a dynamic range larger than 41 dB. Current consumption of the complete receiver is 250 mA from a 1.8 V power supply. 210 mA of the total current is dissipated in the post-amplifier and output buffer.

Two high-speed optical front-ends with integrated photodiodes in standard 0.18 /spl mu/m CMOS

Two optical front-ends implemented in a standard 0.18 /spl mu/m CMOS technology are presented. They differ mainly in layout topology of the photodiode. The front-end with classical n-well diode achieves a bitrate of 300 Mbit/s. At an input power of -8 dBm, the BER is 2/spl times/10/sup -10/. The front-end with differential n-well diode outperforms the classical n-well topology and reaches bitrates up to 500 Mbit/s. At this speed, an input power of -8 dBm is sufficient to have a BER of 3/spl times/10/sup -10/. Both front-ends consume only 17 mW.

A 3.5Gbit/s post-amplifier in 0.18/spl mu/m CMOS

A postamplifier with output buffer implemented in a standard 0.18/spl mu/m 1.8V CMOS technology is proposed. Using broadband techniques for both postamplifier and output buffer, highspeed operation has been achieved. For a differential 10mV/sub pp/ 2/sup 31/-1 pseudo random bit sequence, a bit error rate of 5/spl middot/10/sup -12/ at 3.5Gbit/s has been measured. At lower bitrates the bit error rate is even lower: a 1 Gbit/s 10mV/sub pp/, input signal results in a bit error rate of 7/spl middot/10/sup -14/. The rms jitter is 12ps. The postamplifier circuit consumes only 19mA from a 1.8V power supply.

Digital communication systems: the problem of analog interface circuits

Due to the use of deep sub-micron and nano technologies, the signal processing in the digital area becomes so powerful that the limitations are again situated in the analog front-end circuits. This becomes a huge problem in signal output drivers. The development of xDSL and RF systems all lack efficient power amplifiers, especially if they have to be realized in standard CMOS technologies. Another challenge is the design of wide-band receiver front-ends including low-noise input-matched CMOS amplifiers. An overview of the limitations, trends and some recent achievements from the open literature were analyzed and discussed.

Gigabit photodiodes in standard digital nanometer CMOS technologies

A study of the performance of photodiodes in a fully standard sub 0.1 /spl mu/m technology is presented. A one-dimensional model is developed to get a rough idea of speed and responsivity of the detectors. Next, two-dimensional simulations of two basic unit cells are performed The importance of the side-wall capacitance of a junction is demonstrated, and a clear trade-off between speed and responsivity is shown. According to simulations, the nwell diode can achieve a bitrate of 200 Mbit/s and a responsivity of 0.36 A/W. By considering also the p/sup +/ to nwell junction, a bitrate of 1 Gbit/s and a responsivity of 0.08 A/W can be achieved. Finally, the layout issues of different test diodes are discussed.