Filipe Salgado

Task-Aware Interrupt Controller: Priority Space Unification in Real-Time Systems

In the development of real-time systems, predictability is often hindered by technological factors which break the timing abstractions offered by real time operating systems (RTOSs); namely, the priority space separation between threads and interrupts induces the rate-monotonic problem. Software approaches have tackled this issue, attempting to unify the priority space with varying degrees of success. We present a hardware approach to the problem: unifying the priority space at the interrupt handling subsystem, predictability is greatly enhanced with minimum software modifications. Our solution provides the interrupt controller with awareness of the currently running tasks priority making the solution independent of the used operating system. We show how our approach is minimally intrusive at hardware architecture level and provides benefits beyond the capabilities of previous approaches. Our technique shows a 0.05% run-time overhead if no interrupts occur, and run-time reduction proportional to interrupt rate for rates higher than 5 per s, for a interrupt workload around 0.07 ms.

Building IEEE 802.15.4 Accelerators for Heterogeneous Wireless Sensor Nodes

Bringing IPv6 connectivity to low-end wireless sensor nodes leads to considerable device resources utilization, e.g., central processing unit and energy, caused by the increased amount of data transferred over the network that needs to be handled. In order to reduce these overheads, this letter proposes an IEEE 802.15.4 accelerator for heterogeneous wireless sensor systems that target the Internet of Things sensing applications, which include on the same node, field-programmable gate array technology beside a microcontroller provided with wireless connectivity. The deployed solution implements the Third-level of filtering specified by the standard, and performs basic packet handling such as the detection of multiple receptions of the same frame. The obtained results show the benefits of including such accelerator on the reconfigurable computing unit, offering nearly 17 of overhead reduction. All filtering functionalities are executed by the accelerator to discard unneeded data frames, which avoids unnecessary interrupts to the operating system and increases the system availability up to 59.

CUTE Mote, A Customizable and Trustable End-Device for the Internet of Things

The ubiquitous connectivity of the low-end devices in the Internet of Things (IoT) brings new challenges over the traditional wireless sensor networks’ architectures. Such challenges require not only security and privacy-related features, but also solutions to handle the ever-growing amount of data transferred over the network. However, performing such tasks on resource constrained devices is not straightforward. The need for energy-efficient devices, while preserving their performance and security capabilities, requires new solutions at the architectural level of the wireless device. This paper proposes a heterogeneous architecture that targets low-end and resource constrained IoT devices, combining a hardcore microcontroller unit (MCU) and a reconfigurable computing unit (RCU) with an IEEE 802.15.4 radio transceiver. The MCU hosts an embedded operating system with an IoT-enabled network stack, and exploits the available field-programmable gate array technology to implement the RCU and to deploy customized sensing- and network-related accelerators, offloading heavy, and/or complex software tasks to dedicated hardware blocks. The customizable and trustable end-device mote was implemented using the proposed architecture and the achieved results demonstrates the benefits, both in terms of performance and energy, of accelerating network-related tasks in always-connected resource constrained IoT devices.

Towards an FPGA-based network layer filter for the Internet of Things edge devices

In the near future, billions of new smart devices will connect the big network of the Internet of Things, playing an important key role in our daily life. Allowing IPv6 on the low-power resource constrained devices will lead research to focus on novel approaches that aim to improve the efficiency, security and performance of the 6LoWPAN adaptation layer. This work in progress paper proposes a hardware-based Network Packet Filtering (NPF) and an IPv6 Link-local address calculator which is able to filter the received IPv6 packets, offering nearly 18% overhead reduction. The goal is to obtain a System-on-Chip implementation that can be deployed in future IEEE 802.15.4 radio modules.

Towards hardware embedded virtualization technology: architectural enhancements to an ARM SoC

Embedded virtualization possesses inherent challenges which differentiate the domain from traditional virtualization application fields such as server and desktop computing. Standard software virtualization solutions have a negative impact, not only on memory footprint and performance, but also on determinism and interrupt latency which are critical for the embedded real-time domain. Thus, efficient embedded virtualization requires domain-specific software and hardware support. This paper presents work in progress results of hardware-based Hypervisor implementation. The use cases of embedded virtualization are analyzed, justifying the reasoning for hardware-supported virtualization. Architectural and micro-architectural improvements to an ARM v5TE processor are described, demonstrating the performance advantages, and compared against ARM Virtualization Extensions, identifying respective vulnerabilities and providing alternative solutions which enable higher flexibility, minimizing virtualization costs. The research roadmap towards a hardware-complete Hypervisor, based on the presented results, is described.

Exploring metrics tradeoffs in a multithreading extensible processor

State of the art FPGAs allow the implementation of small to medium sized Systems-on-Chip (SoCs) where configurability is key in order to achieve design goals. Thus, SoCs are frequently designed around soft extensible processors, which provide a tradeoff between design flexibility and fast time to market. This paper presents the impact of micro-architectural features on several design metrics of a multithreading extensible processor. Using the MiBench benchmark, it is shown how Custom Computational Units (CCUs) can significantly increase performance while providing lower power solutions than software-only implementations. An efficient architecture that facilitates the insertion of CCUs is described and the effect of multithreading and thread scheduling policies on the design metrics is also demonstrated. Results show that multithreading policies can have positive impact on key parameters (e.g., up to 20% increase on performance and up to 10% energy savings in the given application), depending on application characteristics as well as micro-architectural features.

A 6LoWPAN Accelerator for Internet of Things Endpoint Devices

The Internet of Things (IoT) is revolutionizing the Internet of the future and the way smart devices, people, and processes interact with each other. Challenges in endpoint devices (EDs) communication are due not only to the security and privacy-related requirements but also due to the ever-growing amount of data transferred over the network that needs to be handled, which can considerably reduce the system availability to perform other tasks. This paper presents an IPv6 over low power wireless personal area networks (6LoWPAN) accelerator for the IP-based IoT networks, which is able to process and filter IPv6 packets received by an IEEE 802.15.4 radio transceiver without interrupting the microcontroller. It offers nearly 13.24% of performance overhead reduction for the packet processing and the address filtering tasks, while guaranteeing full system availability when unwanted packets are received and discarded. The contribution is meant to be deployed on heterogeneous EDs at the network edge, which include on the same architecture, field-programmable gate array (FPGA) technology beside a microcontroller and an IEEE 802.15.4-compliant radio transceiver. Performed evaluations include the low FPGA hardware resources utilization and the energy consumption analysis when the processing and accepting/rejection of a received packet is performed by the 6LoWPAN accelerator.

A PID controller module tightly-coupled on a processor datapath

Control systems are widely used in several industrial applications fields. The most traditional control system, the Proportional, Integrative and Derivative (PID) controller, has long been implemented through several different technologies. In the last two decades, the widespread use of Field Programmable Gate Arrays (FPGAs) led to the development of several dedicated digital hardware PID modules. The integration of such modules on Systems-on-Chip typically attaches PID modules to softcore microprocessors by hanging the former on a peripheral bus which causes area and power overhead. This paper presents a PID module tightly-coupled on a processor datapath. The integration of the system with the processor is described and a test case is presented. Results show the performance levels of FPGA PID controller designs and the advantages of fine-grained customization on system design.

A customizable processor architecture for a design space exploration framework

The design flexibility offered by current Field Programmable Gate Array (FPGA) technology allows system designers to partition application functionalities between hardware and software to meet the design goals such as area, power consumption, etc. Efficient partitioning is a nonpolynomial problem, usually performed by Design Space Exploration (DSE), where certain metrics of the design space must be set by the designer in order to ensure exploration feasibility. This paper describes a customizable processor architecture to be integrated on a DSE tool for Multi-Processor Systems-on-Chip (MPSoCs). The proposed architecture is a multi-threading processor whose micro-architecture can be finetuned and whose ISA can be extended, allowing its use as a processor template for hardware/software co-design. Using benchmarks from the MiBench suite, results on how the performance/area/power tradeoffs are explored by the configuration possibilities are shown, describing the processors several micro-architectural features and how they were designed with configurability as a goal.

A Fault Tolerant Design Methodology for a FPGA-based Softcore Processor

Abstract The susceptibility of digital systems to faults requires the implementation of Fault Tolerant architectures to ensure high-reliability and availability. Field Programmable Gate Arrays are especially sensitive to Single-Event Upsets and Single-Event Transients, since the configuration memory of the chip can be affected, resulting in permanent error; thus, special care must be taken when implementing Fault Tolerant architectures for FPGAs. This paper describes the architecture of a Fault Tolerant softcore processor using triplication of all units as well as using a parity protection scheme for on-chip caches, presenting the impact on area, clock frequency and I/O requirements of both implementations, targeting FPGAs. Experiments show a high fault tolerance and demonstrate the relationship of cache hit rates with fault propagation.