Paulo Garcia

Task-Aware Interrupt Controller: Priority Space Unification in Real-Time Systems

In the development of real-time systems, predictability is often hindered by technological factors which break the timing abstractions offered by real time operating systems (RTOSs); namely, the priority space separation between threads and interrupts induces the rate-monotonic problem. Software approaches have tackled this issue, attempting to unify the priority space with varying degrees of success. We present a hardware approach to the problem: unifying the priority space at the interrupt handling subsystem, predictability is greatly enhanced with minimum software modifications. Our solution provides the interrupt controller with awareness of the currently running tasks priority making the solution independent of the used operating system. We show how our approach is minimally intrusive at hardware architecture level and provides benefits beyond the capabilities of previous approaches. Our technique shows a 0.05% run-time overhead if no interrupts occur, and run-time reduction proportional to interrupt rate for rates higher than 5 per s, for a interrupt workload around 0.07 ms.

A customizable and ARINC 653 quasi-compliant hypervisor

This paper presents a novel hypervisor, developed for aerospace applications using an object oriented approach that embodies time and space partitioning (TSP) on a PowerPC (PPC) core embedded in a FPGA, for the NetworkCentric core avionics [1] - an architecture of cooperating components and managed by a real-time operating system, to implement dependable computing and targeting simplicity. To support Integrated Modular Architecture (IMA) [2] partitioned software architectures, the proposed hypervisor adapted to the aerospace application domain the Popek and Goldbergs [3] fidelity, efficiency and resource control virtualization requirements, and extends them with additional ones like timing determinism, reactivity and improved dependability. A distinctive feature of this hypervisor is its I/O device virtualization approach that guarantees real-time performance and small trusted computing base. The object oriented approach will be particularly useful to customize key components of the hypervisor (with different granularity levels) such as partition scheduling and the communications manager using generative programming techniques (Aspect Oriented Programming (AOP) and template meta-programming).

Towards hardware embedded virtualization technology: architectural enhancements to an ARM SoC

Embedded virtualization possesses inherent challenges which differentiate the domain from traditional virtualization application fields such as server and desktop computing. Standard software virtualization solutions have a negative impact, not only on memory footprint and performance, but also on determinism and interrupt latency which are critical for the embedded real-time domain. Thus, efficient embedded virtualization requires domain-specific software and hardware support. This paper presents work in progress results of hardware-based Hypervisor implementation. The use cases of embedded virtualization are analyzed, justifying the reasoning for hardware-supported virtualization. Architectural and micro-architectural improvements to an ARM v5TE processor are described, demonstrating the performance advantages, and compared against ARM Virtualization Extensions, identifying respective vulnerabilities and providing alternative solutions which enable higher flexibility, minimizing virtualization costs. The research roadmap towards a hardware-complete Hypervisor, based on the presented results, is described.

Exploring metrics tradeoffs in a multithreading extensible processor

State of the art FPGAs allow the implementation of small to medium sized Systems-on-Chip (SoCs) where configurability is key in order to achieve design goals. Thus, SoCs are frequently designed around soft extensible processors, which provide a tradeoff between design flexibility and fast time to market. This paper presents the impact of micro-architectural features on several design metrics of a multithreading extensible processor. Using the MiBench benchmark, it is shown how Custom Computational Units (CCUs) can significantly increase performance while providing lower power solutions than software-only implementations. An efficient architecture that facilitates the insertion of CCUs is described and the effect of multithreading and thread scheduling policies on the design metrics is also demonstrated. Results show that multithreading policies can have positive impact on key parameters (e.g., up to 20% increase on performance and up to 10% energy savings in the given application), depending on application characteristics as well as micro-architectural features.

A PID controller module tightly-coupled on a processor datapath

Control systems are widely used in several industrial applications fields. The most traditional control system, the Proportional, Integrative and Derivative (PID) controller, has long been implemented through several different technologies. In the last two decades, the widespread use of Field Programmable Gate Arrays (FPGAs) led to the development of several dedicated digital hardware PID modules. The integration of such modules on Systems-on-Chip typically attaches PID modules to softcore microprocessors by hanging the former on a peripheral bus which causes area and power overhead. This paper presents a PID module tightly-coupled on a processor datapath. The integration of the system with the processor is described and a test case is presented. Results show the performance levels of FPGA PID controller designs and the advantages of fine-grained customization on system design.

A customizable processor architecture for a design space exploration framework

The design flexibility offered by current Field Programmable Gate Array (FPGA) technology allows system designers to partition application functionalities between hardware and software to meet the design goals such as area, power consumption, etc. Efficient partitioning is a nonpolynomial problem, usually performed by Design Space Exploration (DSE), where certain metrics of the design space must be set by the designer in order to ensure exploration feasibility. This paper describes a customizable processor architecture to be integrated on a DSE tool for Multi-Processor Systems-on-Chip (MPSoCs). The proposed architecture is a multi-threading processor whose micro-architecture can be finetuned and whose ISA can be extended, allowing its use as a processor template for hardware/software co-design. Using benchmarks from the MiBench suite, results on how the performance/area/power tradeoffs are explored by the configuration possibilities are shown, describing the processors several micro-architectural features and how they were designed with configurability as a goal.

A Fault Tolerant Design Methodology for a FPGA-based Softcore Processor

Abstract The susceptibility of digital systems to faults requires the implementation of Fault Tolerant architectures to ensure high-reliability and availability. Field Programmable Gate Arrays are especially sensitive to Single-Event Upsets and Single-Event Transients, since the configuration memory of the chip can be affected, resulting in permanent error; thus, special care must be taken when implementing Fault Tolerant architectures for FPGAs. This paper describes the architecture of a Fault Tolerant softcore processor using triplication of all units as well as using a parity protection scheme for on-chip caches, presenting the impact on area, clock frequency and I/O requirements of both implementations, targeting FPGAs. Experiments show a high fault tolerance and demonstrate the relationship of cache hit rates with fault propagation.

A generative-oriented model-driven design environment for customizable video surveillance systems

To tackle the growing complexity and huge demand for tailored domestic video surveillance systems along with a high demanding time-to-market expectation, engineers at IVV Automação, LDAa are exploiting video surveillance domain as families of systems that can be developed following a pay-as-you-go fashion rather than developing an ex-nihilo new product. Several and different new functionalities are required for each new product’s hardware platforms (e.g., ranging from mobile phone, PDA to desktop PC) and operating systems (e.g., flavors of Linux, Windows and MAC OS X). Some of these functionalities have special economical constraints of development time and memory footprint. To better accommodate all the above listing requirements, a model-driven generative software development paradigm supported by mainstream tools is proposed to offer a significant leverage in hiding commonalities and configuring variabilities across families of video surveillance products while maintaining the new product quality.

A FPGA based C runtime hardware accelerator

As the complexity of embedded systems, as well as the range of applications, grows, the demand for low power high-performance systems also increases. Solutions to address these issues have been presented in the literature, addressing techniques to increase performance by replacing software features, namely RTOS primitives, by hardware implementations. This paper presents an acceleration technique at a lower level: the runtime environment. Hardwiring part of a programming languages runtime environment decreases the required time to perform a task, offering acceleration at a low-level, transparent to higher-level layers. The developed technique was implemented on a FPGA based RISC processor; experimental results showed a decrease in the time required to perform a given task of up to 16%.

Hybrid real-time operating systems: deployment of critical FreeRTOS features on FPGA

Performance and determinism are two critical metrics in most embedded systems with real-time requirements. Owing to the complexity of current embedded systems, along with increased application demands, real-time operating systems (RTOSs) have become a de facto solution providing specific services to the system tasks. However, this extra layer, which abstracts the hardware from the software, makes it harder for a system to achieve good performance and determinism. To ease the impact of a RTOS in the system, RTOS run-time services are offloaded to the hardware layer. This paper presents a hybrid RTOS implementation, where several critical RTOS services were migrated from software to hardware, improving system latency and predictability. Special focus was given to the RTOS scheduler and to the mutexes handling subsystem. The developed hardware accelerators were synthesised on a field-programmable gate array (FPGA), exploiting the point-to-point fast simplex link (FSL) bus to interconnect to the Xilinx Microbaze soft-core processor. Our approach shows that hybrid RTOS has a better performance and predictability when compared to its software-only version.