Florian Erdinger

The DSSC pixel readout ASIC with amplitude digitization and local storage for DEPFET sensor matrices at the European XFEL

The DSSC (DEPFET Sensor with Signal Compression) consortium develops a IMPixel detector for low energy X-rays at the European XFEL. The XFEL will produce 10 bursts per second, each containing 2880 X-ray pulses with a repetition rate of 4.5 MHz. X-ray photons of 0.5 - 6 keV are absorbed in hexagonal DEPFET pixels of 229 × 204 μm2 pitch with a nonlinear characteristic to achieve a high dynamic range. The sensors will be bump bonded to readout ASICs of 64 × 64 pixels. Each pixel contains a filter with trapezoidal weighting function, a single slope ADC of 8-9 Bit resolution and a digital memory to store 640 events. A veto mechanism allows to discard uninteresting events. The digital hit data is read out serially during the ≈100 ms long burst gaps. Prototype matrix chips of 8 × 8 pixels with the full functionality have been produced and characterized electronically and with DEPFET sensors. The architecture and the design of the 8 × 8 ASIC, measured results and an outlook to the large 64 × 64 pixel chip will be presented.

Pixel readout ASIC with per pixel digitization and digital storage for the DSSC detector at XFEL

The DSSC collaboration is developing an instrument for the detection of synchrotron X-rays (E > 0.5 keV) at XFEL. The hexagonal pixels of a DEPFET based sensor with integrated signal compression will be read out by bump-bonded pixel readout ASICs. Each ASIC will have 64 × 64 pixel channels of 236 × 204 μm2 area, each one containing a low-noise (< 50 e−) amplification of the DEPFET signal, an 8 bit single-slope ADC and a digital memory, as well as other blocks for test injection, gain switching and trimming. Data is acquired during the XFEL burst at a rate of up to 4.5 MHz. The signal is first processed by a trapezoidal shaping filter, digitized immediately and then stored to the in-pixel memory of > 512 events capacity. The accumulated digital data is transferred off chip during the 100 ms long burst gaps on a single serial link while the analogue sections are shut down to bring the average power dissipation to < 100 mW per ASIC. The chip architecture is described and results obtained from first test chips are presented.

Characterization of the Flip Capacitor Filter for the XFEL-DSSC Project

The European X-ray Free Electron Laser (XFEL) under construction in Hamburg (Germany) will be able to deliver high intensity X-ray pulses of few tens of femto seconds of duration, at 5 MHz pulse repetition rate. Thanks to its characteristics, this instrument will open up new research opportunities for experiments in femto chemistry, structural biology and material research. A high speed focal plane detector system has been presented, based on a novel non-linear DEPFET as a detector. DEPFETs have been chosen since they can provide excellent energy resolution and high speed readout, a fundamental property to cope with the very demanding pulse time structure of XFEL. Full parallel readout is required, with every channel comprising analog filtering, data conversion and memory storage. In this paper we show results for the first prototype of the analog front end that implements the current readout of the DEPFET pixel. The circuit is based on the Flip Capacitor Filter technique, here briefly presented, and has been designed in 130 nm 1.2 V CMOS technology from IBM. Careful characterization of the individual circuit alone and also connected to a single pixel linear detector has been carried out and the measured performance is summarized.

Calibration of the non-linear system response of a prototype set-up of the DSSC detector for the European XFEL

The DSSC (DEPFET Sensor with Signal Compression) is a new instrument with non-linear compression of the input signal in the sensor and with parallel signal processing (filtering, linear amplification, and digitization) for all pixels. The DSSC will serve as 2d imaging detector at the European X-ray Free Electron Laser (XFEL.EU) currently under construction in Hamburg, Germany. The DSSC design goal is to achieve at the same time single photon detection and high dynamic range of about 104 photons, both for photon energies down to 0.5 keY and read-out speeds up to 4.5 MHz. Realization of this goal requires an accurate calibration of the non-linear system response (NLSR) over the full dynamic range of the detector. We present our strategy for calibrating the NLSR, for each of the 1024 × 1024 DSSC pixels, in the laboratory. The feasibility of our calibration strategy is demonstrated experimentally by calibrating the NLSR of a DSSC prototype set-up consisting of a prototype DEPFET sensor with non-linear signal compression connected to a prototype read-out ASIC.

Fast, low-noise, low-power electronics for the analog readout of non-linear DEPFET pixels

A high speed focal plane system and a novel non linear DEPFET detector are under development to comply with the European X-ray Free Electron Laser (XFEL) requirements. The facility is under construction in the Hamburg area (Germany) and will be able to deliver ultra short, high intensity X-ray pulses 220ns apart and grouped in macro bunches with a repetition rate of 10Hz. DEPFETs have been chosen since they can provide excellent energy resolution and high speed readout. Full parallel readout is required, with every channel comprising analog filtering, data conversion and memory storage. Here we present results for the first prototype of the analog front end stage, that implements a current readout approach. The circuit is based on the Flip Capacitor Filter technique and was realized in 130nm 1.2V CMOS technology from IBM.

Compact digital memory blocks for the DSSC pixel readout ASIC

The European XFEL will have a burst rate of up to 5 MHz arranged in bunch trains each comprising up to 3000 pulses. The inter bunch train rate will be 10 Hz. The pixel readout of the DSSC (DEPFET Sensor with Signal Compression) foreseen for this machine will immediately digitize all analogue charges. The digital data is then stored locally within the pixels before it is read out. In order to accumulate a maximum number of events during the XFEL bunch trains, a compact digital memory solution is required. Relatively slow concepts can be implemented because access times of > 200 ns are required. Readout of the pixel memories will be done in between of the XFEL bunch trains. We have therefore designed and tested two compact storage solutions based on static or dynamic storage in the IBM 130 nm technology, both of them using only three metalization layers within the pixels. The DSSC readout chip will comprise 4096 pixels, each pixel having a size of 229 mm × 204 mm. One third of the pixel has been allocated for the digital storage.

Calibration of the Non-Linear System Characteristic of a prototype of the DSSC detector for the European XFEL

The DEPFET Sensor with Signal Compression (DSSC) will be a 2d imaging detector for the European X-ray Free Electron Laser (XFEL.EU) currently under construction in Hamburg. In order to reach the anticipated detector performance, a precise knowledge of the Non-Linear System Characteristic (NLSC) of the DSSC is needed. The NLSC describes the relation between the signal charge collected in the internal gate of a DEPFET pixel and the respective digital output. It will have to be calibrated prior to each scientific experiment as a function of the XFEL photon energy and the requested photon counting mode. Moreover, each of the 1024 × 1024 DSSC pixels will have to be calibrated individually due to small pixel-to-pixel variations. We present here an overview of the DSSC calibration procedure, a first experimental calibration of the NLSC of a prototype DSSC pixel as well as a first validation of the calibration.

A front-end stage with signal compression capability for XFEL detectors

In this work, we present a front-end stage with signal compression capability to be used in detectors for the new European XFEL in Hamburg. This front-end is an alternative solution under study for the DEPFET Sensor with Signal Compression (DSSC) detection system for the European XFEL. The DEPFET sensor of the DSSC project has a high dynamic range and very good noise performance. The high gain for small collected charge and the compression for large signals will provide both desired features of single photon detection capability and wide dynamic range. However, manufacturing of the DEPFET sensor requires a sophisticated processing technology with a relatively long time fabrication process. Accordingly, an alternative solution, namely Day-0 solution, was introduced as an approach characterized not by the best performance of the DEPFET, but available in a shorter time to allow first beam tests and experiments. The alternative sensor is made of mini Silicon Drift Detector (mini-SDD) and the compression behavior is obtained from the front-end on the readout ASIC and not by the transistor integrated in the silicon sensor, as in the DEPFET. The first version of corresponding front-end of the Day-0 solution has been realized based on an input PMOSFET transistor placed on the readout chip. This simple front-end proved the working principle of the proposed compression technique and the desired noise performance. In this paper, an improved version of the Day-0 front-end is presented. In the new prototype, the current gain of the front-end stage has been increased by factor of 1.8, the total input capacitance (SDD+PMOSFET) has been reduced by factor of 2 with respect to the previous prototype and consequently the noise performance has been improved. Moreover, by introducing selectable extra branches in parallel with the main one, the compression behavior of the front-end can be tuned based on desired dynamic range.

A 5MHz low-noise 130nm CMOS analog front-end electronics for the readout of non-linear DEPFET sensor with signal compression for the European XFEL

We present an integrated analog front-end for the readout of a non-linear DEPFET Sensor with Signal Compression (DSSC). The DSSC system, currently under development, is a 1-Mega pixel detector system for the European X-ray Free Electron Laser (XFEL) in Hamburg. It will record X-ray images with a maximum frame rate of 4.5MHz and will achieve at the same time a single photon resolution at 1keV and a high dynamic range. Two different readout strategies of the DEPFET pixel, Source Follower (SF) and Drain Readout (DR), have been fabricated in the 1.2V 0.13μm IBM CMOS technology. Both solutions share the same analog filter based on a new architecture that implements a trapezoidal shaping function employing only one operational amplifier. In this paper, the architecture of the analog front-end relative to both the readout strategies and of the new designed filter and the performance of the test chips are presented.

Study of PMOS front-end solution with signal compression for XFEL MiniSDD X-ray detectors

In this work we present the study and the experimental results on two different front-end stages for the MiniSDD pixel sensors of the DSSC detector for photon science applications at the European XFEL GmbH in Hamburg. The detector must be able to cope with an image frame rate up to 4.5 MHz and must achieve a dynamic range up to 104 photons/pixel/pulse with a photon energy of 1 keV. In order to achieve this high dynamic range and single photon sensitivity at the same time, the front-end must provide a non-linear amplification. The non-linear response is obtained with a simple circuit that pushes the input PMOSFET into triode region as the input signal increases. Since the readout ASIC has more than 4000 channels operating in parallel, particular care was devoted to the homogeneity and the robustness of the implemented solution, especially with respect to power supply rejection ratio and the cross talk among channels.