Florian Kluge

Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability

The Merasa project aims to achieve a breakthrough in hardware design, hard real-time support in system software, and worst-case execution time analysis tools for embedded multicore processors. The project focuses on developing multicore processor designs for hard real-time embedded systems and techniques to guarantee the analyzability and timing predictability of every feature provided by the processor.

parMERASA -- Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability

Engineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in performance is expected by parallelizing hard real-time applications and running them on an embedded multi-core processor, which enables combining the requirements for high-performance with timing-predictable execution. parMERASA will provide a timing analyzable system of parallel hard real-time applications running on a scalable multicore processor. parMERASA goes one step beyond mixed criticality demands: It targets future complex control algorithms by parallelizing hard real-time programs to run on predictable multi-/many-core processors. We aim to achieve a breakthrough in techniques for parallelization of industrial hard real-time programs, provide hard real-time support in system software, WCET analysis and verification tools for multi-cores, and techniques for predictable multi-core designs with up to 64 cores.

RTOS Support for Parallel Execution of Hard Real-Time Applications on the MERASA Multi-core Processor

Multi-cores are the contemporary solution to satisfy high performance and low energy demands in general and embedded computing domains. However, currently available multi-cores are not feasible to be used in safety-critical environments with hard real-time constraints. Hard real-time tasks running on different cores must be executed in isolation or their interferences must be time-bounded. Thus, new requirements also arise for a real-time operating system (RTOS), in particular if the parallel execution of hard real-time applications should be supported. In this paper we focus on the MERASA system software as an RTOS developed on top of the MERASA multi-core processor. The MERASA system software fulfils the requirements for time-bounded execution of parallel hard real-time tasks. In particular we focus on thread control with synchronisation mechanisms, memory management and resource management requirements. Our evaluations show that all system software functions are time-bounded by a worst-case execution time (WCET) analysis.

Exploiting spare resources of in-order SMT processors executing hard real-time threads

We developed an SMT processor that allows a static WCET analysis of several hard real-time threads and uses the remaining resources for soft or non real-time threads. The analysis is possible, because one Dominant Meta Thread (DMT) is executed as if it were the unique thread on the processor and thus single-threaded WCET techniques can be applied. To provide more than one hard real-time thread the execution time of the Dominant Meta Thread is distributed by time sharing whereby the length of the time slices and periods can be adjusted at runtime. Our technique, called Dominant Time Sharing (DTS), can be used to minimize the number of control units in embedded hard real-time systems and hence reduces the overall energy consumption and material demand. In contrast to many other studies we are able to handle multicycle memory latencies while preserving analyzability. The proposed technique can easily be extended to access other external resources like coprocessors or reconfigurable arrays.

Time analysable synchronisation techniques for parallelised hard real-time applications

In this paper we present synchronisation techniques for hard real-time (HRT) capable execution of parallelised applications on embedded multi-core processors. We show how commonly used software synchronisation techniques can be implemented in a time analysable way based on the proposed hardware primitives. We choose to implement the hardware synchronisation primitives in the memory controller for two reasons. Firstly, we remove pessimism in the WCET analysis of parallelised HRT applications. Secondly, we enable that the implementation of synchronisation techniques is mostly independent of the chosen instruction set architecture (ISA) which allows to use the existing ISAs without enhancements. We analyse the presented synchronisation techniques with the static worst-case execution time (WCET) analysis tool OTAWA. In summary, our specifically engineered synchronisation techniques yield a tremendous gain on the WCET of parallelised HRT applications.

A Two-Layered Management Architecture for Building Adaptive Real-Time Systems

The concepts of Autonomic and Organic Computing (AC/OC) promise to make modern computer systems more secure and easier to manage. In this paper, we extend the observer/controller architecture typically used in AC/OC systems towards a new target area --- embedded real-time systems. As a result we present a two-layered management architecture. We discuss aspects of internal communication and design a communication model. Finally, we present a generic classification system for the upper layer of the management architecture.

Organic Computing Middleware for Ubiquitous Environments

The complexity of computer systems has been increasing during the past years. To control this complexity organic computing introduces the self-x features. The Organic Computing Middleware for Ubiquitous Environments eases to manage distributed computing systems by using self-configuration, self-optimisation, self-healing and self-protection. To provide these self-x features the latest version of our middleware uses an Observer/Controller architecture with an automated planner. Planning is time consuming so we introduced additionally reflexes for faster reactions. The reflexes are learned from previous plans and can be distributed to resource restricted nodes.

The Neighbor-Trust Metric to Measure Reputation in Organic Computing Systems

Reputation is an important aspect of trust. If no direct trust experiences are available, one needs to rely on reputation data from other sources. In this paper we present the Neighbor-Trust metric that exploits these communication capabilities of a network by directly asking all neighbors of a target communication partner for reputation trust data. This results in a reputation path of length one, but also in a vulnerability to attacks by unknown, lying entities that try to promote not trustworthy entities. However, by adding weights for reputation data given by entities and a learning mechanism the Neighbor-Trust metric is able to identify and adapt to lying participants in the network by reducing the weight their reputation data has in future reputation calculations. We present an evaluation for the metric and show how to exclude lying participants from the network.

Implementing AUTOSAR scheduling and resource management on an embedded SMT processor

The AUTOSAR specification provides a common standard for software development in the automotive domain. Its functional definition is based on the concept of single-threaded processors. Recent trends in embedded processors provide new possibilities for more powerful processors using parallel execution techniques like multithreading and multi-cores. We discuss the implementation of the AUTOSAR operating system interface on a modern simultaneous multithreaded (SMT) processor. Several problems in resource management arise when AUTOSAR tasks are executed concurrently on a multithreaded processor. Especially deadlocks, which should be averted through the priority ceiling protocol, can reoccur. We solve this problems by extending AUTOSAR OS by the Task Filtering Method to avoid deadlocks in multithreaded processors. Other synchronisation problems arising through the parallel execution of tasks are solved through the use of lock-free data structures. In the end, we propose some extensions to the AUTOSAR specification so it can be used in software development for SMT processors. We develop some additional requirements on such SMT processors to enable the use of the Task Filtering Method. Our work gives also perspectives for software development on upcoming multi-core processors in the automotive domain.

Optimisations for LocSens – an indoor location tracking system using wireless sensors

Ubiquitous and pervasive computing envisions context-aware systems that gather real-world information from many fixed and mobile microchips and sensors integrated in everyday objects. To provide valuable services, it is necessary to estimate the location of users or objects. Outdoor location tracking is achieved by Global Positioning System (GPS), but due to its poor indoor coverage, there is a need for alternative technologies in buildings. Since multiple wireless sensors may be situated in the environment, they can be used for location estimation and tracking. This paper presents LocSens, a cost-effective location tracking system based on sensor nodes with wireless connectivity. LocSens works with a minimum number of sensor nodes. It is established and tested in a real indoor scenario over multiple rooms. LocSens could be improved by optimising algorithms and using more precise sensor boards. Results confirm gained accuracy in location estimation and tracking of moving objects.