Sascha Uhrig

Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability

The Merasa project aims to achieve a breakthrough in hardware design, hard real-time support in system software, and worst-case execution time analysis tools for embedded multicore processors. The project focuses on developing multicore processor designs for hard real-time embedded systems and techniques to guarantee the analyzability and timing predictability of every feature provided by the processor.

Real-time event-handling and scheduling on a multithreaded Java microcontroller

Abstract Our aim is to investigate the suitability of hardware multithreading for real-time event handling in combination with appropriate real-time scheduling techniques. We designed and evaluated a multithreaded microcontroller based on a Java processor core. Java threads are used as Interrupt Service Threads (ISTs) instead of the Interrupt Service Routines (ISRs) of conventional processors. Our proposed Komodo microcontroller supports multiple ISTs with zero-cycle context switching overhead. A so-called priority manager implements several real-time scheduling algorithms in hardware. We show the feasibility of a hardware real-time scheduler integrated deeply into the processor pipeline with a VHDL design and its synthesis. Evaluations with a software simulator and real-time applications as benchmarks show that hardware multithreading reaches a 1.2–1.4 performance increase for hard real-time applications (multithreading without latency utilization) and a 2.0–2.6 speedup by latency utilization for programs without hard real-time requirements. With respect to real-time scheduling on a multithreaded microcontroller, the Least Laxity First (LLF) scheme outperforms the Fixed Priority Preemptive (FPP), Earliest Deadline First (EDF), and Guaranteed Percentage (GP) schemes, but suffers from the highest implementation costs.

jamuth: an IP processor core for embedded Java real-time systems

This paper proposes a Java multithreaded processor core for embedded real-time systems, jamuth. The processor core is an enhancement of the earlier developed multithreaded Java processor named Komodo. It features a real-time capable incremental garbage collection, integrated real-time scheduling schemes and full compatibility to the Java CDC standard. Hence, it is suitable for embedded hard, soft, and non real-time systems. Due to its design as an IP core for Alteras System-on-Programmable-Chip (SoPC) environment, it can easily be combined with other (peripheral) components to a whole system on a single chip. Additionally, the usage of Java decreases the effort of software development and maintenance in a significant way. In this paper, we evaluate the performance and the utilization as well as the real-time capabilities of the jamuth IP core.

parMERASA -- Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability

Engineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in performance is expected by parallelizing hard real-time applications and running them on an embedded multi-core processor, which enables combining the requirements for high-performance with timing-predictable execution. parMERASA will provide a timing analyzable system of parallel hard real-time applications running on a scalable multicore processor. parMERASA goes one step beyond mixed criticality demands: It targets future complex control algorithms by parallelizing hard real-time programs to run on predictable multi-/many-core processors. We aim to achieve a breakthrough in techniques for parallelization of industrial hard real-time programs, provide hard real-time support in system software, WCET analysis and verification tools for multi-cores, and techniques for predictable multi-core designs with up to 64 cores.

How to enhance a superscalar processor to provide hard real-time capable in-order SMT

This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-time applications. For superscalar in-order architectures the calculation of the Worst Case Execution Time (WCET) is much easier and tighter than for out-of-order architectures. By a careful enhancement that completely isolates the threads, this capability can be perpetuated to an in-order SMT architecture. Our design goal is to minimise the WCET of the highest priority thread, while releasing as many resources as possible for the execution of concurrent non critical threads. The resultant processor executes hard real-time threads at the same speed as its singlethreaded ancestor, but idle issue slots are dynamically used by non critical threads. The modifications to enable SMT are demonstrated by CarCore, a multithreaded embedded processor that implements the Infineon Tricore instruction set.

Hardware-based power management for real-time applications

This paper presents a new power management technique integrated into a multithreaded microcontroller with built-in real-time scheduling schemes. Power management is done by hardware based on the Guaranteed Percentage scheduling scheme. The applied power saving mechanisms are frequency reduction, dynamic voltage scaling and pipeline gating. Our evaluation showed that for a given workload with an average processor utilization of 22.6% and a frequent change of utilization in the range of 0% to 58% energy consumption could be reduced to 12.7% of the energy required by a system running at top speed.

The embedded Java benchmark suite JemBench

Requirements to embedded systems increase steadily. In parallel, also the performance of the processors used in these systems is improved leading to multithreaded and/or multicore architectures. Depending on the type of the embedded system, using Java is a more and more popular way for software development. In this paper, we present a Java benchmark suite that enables the comparison of different embedded Java platforms while solely assuming the availability of a CLDC API, the minimal configuration defined for the J2ME. The core of the benchmark suite consists of adapted real-world applications. Furthermore, the suite contains benchmarks to explore multi-core/multi-threaded systems. Hence, it is possible to determine the gain of a parallel execution platform compared to sequential execution. Additionally, the penalty of a sequential program running on a parallel platform can be measured. Our benchmarks are structured in micro, kernel, application, parallel, and streaming benchmarks.

RTOS Support for Parallel Execution of Hard Real-Time Applications on the MERASA Multi-core Processor

Multi-cores are the contemporary solution to satisfy high performance and low energy demands in general and embedded computing domains. However, currently available multi-cores are not feasible to be used in safety-critical environments with hard real-time constraints. Hard real-time tasks running on different cores must be executed in isolation or their interferences must be time-bounded. Thus, new requirements also arise for a real-time operating system (RTOS), in particular if the parallel execution of hard real-time applications should be supported. In this paper we focus on the MERASA system software as an RTOS developed on top of the MERASA multi-core processor. The MERASA system software fulfils the requirements for time-bounded execution of parallel hard real-time tasks. In particular we focus on thread control with synchronisation mechanisms, memory management and resource management requirements. Our evaluations show that all system software functions are time-bounded by a worst-case execution time (WCET) analysis.

Predictable dynamic instruction scratchpad for simultaneous multithreaded processors

For precise timing analysis of hard-real applications a predictable memory system is of particular importance. Caches have a great impact on performance, but at the cost of reduced timing predictability. Conventional scratchpads, i.e. statically managed on-chip memories, provide predictable memory accesses, but they are usually badly utilized. Better memory utilization is allowed by dynamically managed scratchpads that are designed for predictability. In this paper we propose a function scratchpad that is dynamically managed in hardware and provides a predictable timing behavior. The function scratchpad exploits a simultaneous multithreaded architecture to increase the pipeline and memory bandwidth utilization while preserving predictability.

Toward a processor core for real-time capable autonomic systems

This paper proposes a processor core that allows to support the autonomic computing principles in embedded hard-real-time systems. The simultaneous multithreaded CAR-core processor features hardware-integrated scheduling schemes that isolate the hard-real-time thread from non-real-time threads. It is binary compatible with Infineons TriCore processor and designed as IP core for a system-on-chip. The challenge for the processor design is to implement simultaneous multithreading such that a thread cannot influence the timing behavior of another thread in order to allow predictable thread execution times. Therefore new instruction issue and data memory access techniques are proposed. The autonomic computing requirements shall be implemented by autonomic managers running as helper threads in own thread slots concurrent to the real-time application. The autonomic manager threads monitor the application and decide if self-configuration, self-healing, self-optimization, or self-protection must be triggered