Florian Thoma

MORPHEUS: Heterogeneous Reconfigurable Computing

Reconfigurable architectures and NoC (network-on-chip) communication systems have introduced new research directions for technology and flexibility issues, which have been largely investigated in the last decades. Exploiting the flexibility of reconfigurable architectures, the run-time adap-tivity through run-time reconfiguration, opens a new area of research by considering dynamic reconfiguration. Since software parts of an embedded system can also be included into reconfigurable hardware by integration of an IP-based microcontroller, the reconfigurable architecture provides a flexible, multi-adaptive heterogeneous platform forHW/SW co-design. In this paper, we present the European integrated project MORPHEUS (1ST 027342). Its goal is to develop new heterogeneous reconfigurable SoCs with various sizes of reconfiguration granularity and to provide an integrated toolset of spatial and sequential design that can be used for mapping and execution of the target applications. Additionally a NoC approach is included in order to demonstrate the mentioned benefits and scalability for actual and future SoC design. The power of this approach will be demonstrated with four applications from the industrial environment.

REFLECT: Rendering FPGAs to Multi-core Embedded Computing

The relentless increase in capacity of Field-Programmable Gate-Arrays (FPGAs) has made them vehicles of choice for both prototypes and final products requiring on-chip multi-core, heterogeneous and reconfigurable systems. Multiple cores can be embedded as hard- or soft-macros, have customizable instruction sets, multiple distributed RAMs and/or configurable interconnections. Their flexibility allows them to achieve orders of magnitude better performance than conventional computing systems via customization. Programming these systems, however, is extremely cumbersome and error-prone and as a result their true potential is only achieved very often at unreasonably high design efforts. This project covers developing, implementing and evaluating a novel compilation and synthesis system approach for FPGA-based platforms. We rely on Aspect-Oriented Specifications to convey critical domain knowledge to a mapping engine while preserving the advantages of a high-level imperative programming paradigm in early software development as well as program and application portability. We leverage Aspect-Oriented specifications and a set of transformations to generate an intermediate representation suitable to hardware mapping. A programming language, LARA, will allow the exploration of alternative architectures and design patterns enabling the generation of flexible hardware cores that can be easily incorporated into larger multi-core designs. We will evaluate the effectiveness of the proposed approach using partner-provided codes from the domain of audio processing and real-time avionics. We expect the technology developed in REFLECT to be integrated by our industrial partners, in particular by ACE, a leading compilation tool supplier for embedded systems, and by Honeywell, a worldwide solution supplier of embedded high-performance systems.

A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime Core Fusion

Hardware virtualization is a well known technique in processor based hardware architectures for abstraction of the complexity of an underlying hardware from the programmer. Not only processor based hardware, especially Field Programmable Gate Arrays (FPGA), comes with a high complexity and the exploitation for developers suffer from this fact. Each change in the hardware e.g. through an introduction of a new series results in a re-design of the applications. Therefore, a novel concept for FPGA hardware virtualization is introduced in this paper. The advantage with this approach is that the specification of the virtual FPGA stays unchanged, independent from the underlying hardware and provides therefore features, which the exploited physical host FPGA cannot provide. A special feature of the presented virtual FPGA amongst others is the dynamic reconfigurability which is for example not available with all off the shelf FPGAs. Furthermore the concept of FPGA virtualization enables the re-use of hardware blocks on other physical FPGA devices. This paper presents the hardware platform, describes the tool chain for the virtual FPGA and introduces with Core Fusion a novel technique that improves the utilization of the virtual FPGA.

Dynamic Processor Reconfiguration

General purpose processors provide a well performance with adequate power consumption for a huge bandwidth of applications in average. However, most embedded systems target a very narrow or even single application domain which would benefit from a specific processor, optimized for this scenario in order to gain performance and to reduce power consumption. But the development of application specific processors for each application is a time consuming task and often not feasible for developers due to the missing toolsets or experience in processor design. This paper introduces a novel approach for a processor core, which is able to adapt its micro architecture in relation to the application requirement. In general, the processor starts in a general purpose mode and migrates while run-time to a special purpose processor by adapting its micro architecture. The paper introduces this novel processor approach which is called i-core and presents first experimental results.

LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture

In todays mobile computers, such as tablets and smart phones, power, performance and chip area are the major constraints to the development of cost efficient high tech products. One solution is the usage of application-specific instruction-set processors (ASIP), which are optimized for the execution of special tasks and thus enable a more efficient implementation. As an extension to this approach the LISPARC processor is developed. For more flexibility, the LISPARC model enables dynamic reconfiguration at run-time in order to adapt to different ASIPs. The processor model of LISPARC is described using an architecture description language called Language for Instruction-Set Architectures (LISA).

On Dynamic Run-time Processor Pipeline Reconfiguration

Adaptation of hardware in relation to the requirements of a specific application is well known and investigated in the domain of Field Programmable Gate Arrays (FPGA) based reconfigurable system architectures. In these system approaches, a number of predefined blocks, mainly accelerators for processors, are loaded from an external storage and are transferred to the FPGA configuration memory in order to manipulate the on-chip functionality. A novel approach is to adapt the micro architecture of a processor in order to achieve a temporal application-specific behavior. In combination with the well known techniques of dynamic reconfiguration of a FPGA, novel degrees of freedom are available for an energy efficient run-time dynamic system approach. This paper presents one adaptation mechanism, in which the pipeline depth is adapted according to the control flow and data flow of an application. The concept and also the realization are described and evaluated in terms of efficiency with some benchmarks.

Control of Dynamic Reconfiguration

This Chapter describes the mechanisms used to control the dynamic reconfiguration aspects of the MORPEUS system. The base is formed by real-time operating system and is topped by a allocation and scheduling system for reconfigurable operations.