Fernando M. Gonçalves

IC DEFECTS-BASED TESTABILITY ANALYSIS

High quality IC design involves not only performance and silicon area, but also testability. Product quality, measured by low dejects levels (as low as 100 p.p.m.), requires that test patterns must detect nearly all circuit faults caused by likely physical defects. This requires a careful examination of the testability of the physical design, and its enhancement. The purpose of this contribution is to present a methodology for physical testability evaluation, and to demonstrate its usefulness. The methodology allows realistic fault extraction and classification, and the identification of hard to detect faults, their layout location and physical origin, prior to simulation. Measures of physical testability and fault hardness are introduced. When possible, suggestions for design improvement by layout reconfiguration, are provided, as a better solution than simple test improvement, either by test pattern refinement, or by using more sophisticated detection techniques, like current testing. Simulation results, with several design examples, show that layout styles exhibit characteristic pat.terns, in terms of t,he incidence of faults caused by the different, physical defects. Hence, for each layout style, the sensivity of physical designs to each physical defect can be analysed and decreased. Moreover, simulation results with a new cell library demonstrate that physical design improvements can significantly enhance the circuit’s qualit,y and testability.

Defect level evaluation in an IC design environment

The purpose of this paper is to present a methodology for the evaluation of the Defect Level in an IC design environment. The methodology is based on the extension of Williams-Brown formula to nonequiprobable faults, which are collected from the IC layout, using the information on a typical IC process line defect statistics. The concept of weighted fault coverage is introduced, and the Defect Level (DL) evaluated for the Poisson and the negative binomial yield models. It is shown that DL depends on the critical areas associated with undetected faults, and their correspondent defect densities. Simulation results are presented, which highlight that the classic single Line Stuck-At (LSA) fault coverage is a unreliable metric of test quality. Moreover, results show that the efficiency of a given set of test patterns strongly depends on the physical design and defect statistics.

Wine tartaric stabilization by electrodialysis and its assessment by the saturation temperature

Abstract This investigation of electrodialysis is carried to assess the potassium hydrogen tartrate (KHT) removal for wine tartaric stabilization. The tartaric stability is assessed through the wine saturation temperature. The extent of KHT removal is varied depending on the duration of the electrodialysis up to 24%. The removal of the cations K + , Na + , Ca 2+ and Mg 2+ and of the anions corresponding to tartaric, malic, and lactic acids was monitored. The experiments were performed in a pilot scale electrodialyser with 28 dm 2 of membrane area. Wine saturation temperatures varied linearly with the deionization. For the white wine, a saturation temperature of 14.8 °C and stability up to 0 °C was achieved for a deionization of 14.5% and tartaric acid removal of 10.9%. The lactic and malic acids contents were kept almost constant and the calcium content reduced by 39%. The red wine displayed, without any treatment, a low saturation temperature of 9.2 °C associated to a stable wine.

A methodology for testability enhancement at layout level

In order to make possible the production of cost-effective electronic systems, integrated circuits (ICs) need to be designed for testability. The purpose of this article is to present a methodology for testability enhancement at the lower levels of the design (i.e., at circuit and layout levels). The proposed strategy uses both hardware refinement and software improvement. The main areas of low-cost software improvement are test generation based on a logic description closely related to the physical design, test-vector sequencing, and the introduction of circuit knowledge in fault simulation. The strategy for hardware improvement is based on realistic fault list generation, fault classification (according to fault impact on circuit behavior), and layout-level DFT (design for testability) rules derivation. A preliminary fault classification is proposed, which uncovers the types of realistic faults in MOS digital ICs that are hard to detect, paving the way to derive layout rules for hard-fault avoidance. Simulation examples are presented ascertaining that specific subsets of line-open and bridging faults (according to their topological characteristics) are hard to detect by logic testing using test patterns derived for line stuck-at fault detection.

Integrated approach for circuit and fault extraction of VLSI circuits

The purpose of this paper is to present a methodology for circuit and realistic fault extraction, and its implementation in a new tool, under development. To be included in a virtual test environment, DOTLab. Digital, analog and mixed signal ICs, implemented in CMOS, bipolar or BiCMOS technologies are handled, both in Manhattan and 45/spl deg/ geometries. For complex circuits, higher level information, obtained in the top-down design flow, is used for fault characterization. A sliding window algorithm previously used for circuit extraction, is extended for fault extraction of non-orthogonal geometries.

Physical DFT for High Coverage of Realistic Faults

Test quality requires the ability of test patterns to cover realistic faults originated by physical defects induced during IC manufacturing. Recent progress in a methodology for physical testability analysis is reported in this paper. A refined bridging faults classification provides evidence that reconvergent fan-out areas should be carefully designed to avoid hard to detect faults. Moreover, the concept of selective decompaction is introduced, to show that with reduced area overhead, testability can significantly be increased. As a result, guidelines for cell library development, and for refined routing algorithms, are presented. The results are il1ustra.ted with several design examples. These examples also show that the realistic fault coverage can be higher or lower than the Line Stuck-At (LSA) fault coverage depending on the relative incidence of bridging and open faults, and the topological characteristics of the surrounding circuit.

Physical design of testable CMOS digital integrated circuits

A methodology for physical testability assessment and enhancement, implemented with a set of test tools, is presented. The methodology, which can improve the physical design of testable CMOS digital ICs, is supported in realistic fault-list generation and classification. Two measures of physical testability, weighted class fault coverage and fault incidence, and one measure of fault hardness are introduced. The testability is evaluated prior to fault simulation; difficult-to-detect faults are located on the layout and correlated with the physical defects which originate them; and suggestions for layout reconfiguration are provided. Several design examples are described, ascertaining the usefulness of the proposed methodology. The proposed methodology demonstrated that stuck-at test sets only partially cover the realistic faults in digital CMOS designs. Moreover, it is shown that classical fault models of arbitrary faults are insufficient to describe the realistic fault set. Simulation results have shown that the fault set strongly depends on the technology and on the layout style. >

Fault modeling and defect level projections in digital ICs

This paper presents a new model for evaluating the defect level, DL, in VLSI circuits as a function of the yield, Y, and the stuck-at fault coverage, T. It is shown that the observed DL(T) curve can be accurately modeled using non equally probable, realistic faults predicted from defect statistics data and IC layout. The deviation of DL(T) from the one estimated by the Williams-Brown equation is shown, to be caused by two effects. First, the topology of the most likely realistic faults determine their susceptibility, which is typically lower than the stuck-at fault susceptibility. Second, the incompleteness of a given test set and the detection technique (such as static voltage testing) determine a non 100% defect coverage. The suitability of the model was assessed by means of layout fault extraction and switch-level fault simulation, and the results obtained agree with previously published DL(T) experimental results on actual ICs.<<ETX>>

White wine clarification by micro/ultrafiltration: effect of removed colloids in tartaric stability

Abstract A white wine was clarified by tangential microfiltration (MF) and ultrafiltration (UF). The permeation experiments were carried out in a Dow Lab-unit M20 with a membrane area of 0.036 m 2 . Two membranes were tested, one of MF with a pore size of 1.0 μm and another of UF with a molecular weight cut-off (MWCO) of 100 kDa. They are both made of a fluor polymer and supplied by DSS-Denmark. The operating conditions (pressure and circulation flow rate) were optimised for both membranes. The MF and UF clarification experiments were performed at the same optimal conditions of 1×10 5 Pa transmembrane pressure and 554 l h −1 circulation flowrate. The results were compared in terms of permeate productivity, particle and polysaccharide removal. The polysaccharides were precipitated from the raw wine, the UF permeate and the UF concentrate. Potassium hydrogen tartrate crystallisation induction times were measured at 0°C using hydroalcoholic solutions with and without these polysaccharides. MF and UF presented similar permeate productivities and particle removal. The UF membrane proved to be easier to clean. Polysaccharide removal was low with both membranes: 10% for MF and 16% for UF. The polysaccharides retained by UF did not alter significantly the potassium hydrogen tartrate crystallisation induction times. These induction times are similar for the model solution with the polysaccharides from the raw wine and the UF clarified wine.

Defect-oriented Verilog fault simulation of SoC macros using a stratified fault sampling technique

The validation of high-quality tests requires defect-oriented (DO) fault simulation. The purpose of this paper is to propose a methodology for mixed-level DO Verilog fault simulation. A novel tool, veriDOF, is introduced. Structural zooming is performed only for the system module in which the faults are injected. Verilog models for bridging and line open defects are proposed for intra-gate and inter-gate faults, using a pre-computed test view of each library cell. A stratified fault sampling technique is used to boost the computational efficiency of the new tool. Results are presented for ISCAS benchmarks and a public domain processor, PIC.