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Analyzing synchronous dataflow scenarios for dynamic software-defined radio applications

Contemporary embedded systems for wireless communications support various radios. A software-defined radio (SDR) is a radio implemented as concurrent software processes that typically run on a multiprocessor system-on-chip (MPSoC). SDRs are real-time streaming applications with throughput requirements. One efficient approach for timing analysis of concurrent real-time applications is the dataflow model of computation (MoC). Nonetheless, the dataflow modeling of SDRs is challenging due to their dynamically changing data processing workload. A dataflow MoC that is not expressive enough to capture this dynamism gives pessimistic throughput results. On the other hand, if it is too expressive and detailed, it may not be analyzable at all. In this paper, we address the challenge of dataflow modeling of SDRs such that their timing behavior can be accurately analyzed to guarantee real-time requirements without unnecessarily over-allocating MPSoC resources. The basis of our modeling approach is splitting the dynamic data processing behavior of a SDR into a group of static modes of operation. Each static mode of operation is then modeled by a Synchronous Dataflow (SDF), which we refer to as scenario. This paper has two main contributions: 1) a scenario-based dataflow model of Long Term Evolution (LTE), which is the latest standard in cellular communication, and 2) investigation of existing throughput analysis techniques of SDF scenarios for our LTE model. Our results show that scenario-based worst-case throughput computation is 2 to 3.4 times more accurate than a state-of-the-art SDF analysis technique. Our investigation also shows that existing timing analysis techniques of SDF scenarios have very low run-time that scales very well with increase in graph size. This makes SDF scenarios suitable in practice for modeling and analyzing SDRs as well as similar dynamic applications.

Worst-case throughput analysis of real-time dynamic streaming applications

Wireless embedded applications have stringent temporal constraints. The frame arrival rate imposes a throughput requirement that must be satisfied. These applications are often dynamic and streaming in nature. The FSM-based Scenario-Aware Dataflow (FSM-SADF) model of computation (MoC) has been proposed to model such dynamic streaming applications. FSM-SADF splits a dynamic system into a set of static modes of operation, called scenarios. Each scenario is modeled by a Synchronous Dataflow (SDF) graph. The possible scenario transitions are specified by a finite-state machine (FSM). FSM-SADF allows a more accurate design-time analysis of dynamic streaming applications, capitalizing on the analysability of SDF. However, existing FSM-SADF analysis techniques assume 1) scenarios are self-timed bounded, for which strong-connectedness is a sufficient condition, and 2) inter-scenario synchronizations are only captured by initial tokens that are common between scenarios. These conditions are too restrictive for many real-life applications. In this paper, we lift these restrictive assumptions and introduce a generalized FSM-SADF analysis approach based on the max-plus linear systems theory. We present both exact and conservative worst-case throughput analysis techniques that have varying levels of accuracy and scalability. The analysis techniques are implemented in a publicly available dataflow analysis tool and experimentally evaluated with different wireless applications.

MAMPSx: A design framework for rapid synthesis of predictable heterogeneous MPSoCs

Heterogeneous Multiprocessor System-on-Chips (HMPSoC) are becoming popular as a means of meeting energy efficiency requirements of modern embedded systems. However, as these HMPSoCs run multimedia applications as well, they also need to meet real-time requirements. Designing these predictable HMPSoCs is a key challenge, as the current design methods for these platforms are either semi-automated, non-predictable, or have limited heterogeneity. In this paper, we propose a design framework to generate and program HMPSoC designs in a rapid and predictable manner. It takes the application specifications and the architecture model as input and generates the entire HMPSoC, for FPGA prototyping, that meets the throughput constraints. The experimental results show that our framework can provide a conservative bound on the worst-case throughput of the FPGA implementation. We also present results of a case study that computes the area-power trade-offs of an industrial vision application. The entire design space exploration of all configurations was completed in 8 hours. A tool-chain targeting the Xilinx Zynq FPGA is also presented.

An automated flow to map throughput constrained applications to a MPSoC

This paper describes a design flow to map throughput constrained applications on a Multi-processor System-on-Chip (MPSoC). It integrates several state-of-the-art mapping and synthesis tools into an automated tool flow. This flow takes as input a throughput constrained application, modeled with a synchronous dataflow graph, a C-based implementation for each actor in the graph, and a template based architecture description. Using these inputs, the tool flow generates an MPSoC platform tailored to the application requirements and it subsequently maps the application to this platform. The output of the flow is an FPGA programmable bit file. An easily extensible template based architecture is presented, this architecture allows fast and flexible generation of a predictable platform that can be synthesized using the presented tool flow. The effectiveness of the tool flow is demonstrated by mapping an MJPEG-decoder onto our MPSoC platform. This case study shows that our flow is able to provide a tight, conservative bound on the worst-case throughput of the FPGA implementation. The presented tool flow is freely available at http://www.es.ele.tue.nl/mamps.

Symbolic Analysis of Dataflow Applications Mapped onto Shared Heterogeneous Resources

Embedded streaming applications require design-time temporal analysis to verify real-time constraints such as throughput and latency. In this paper, we introduce a new analytical technique to compute temporal bounds of streaming applications mapped onto a shared multiprocessor platform. We use an expressively rich application model that supports adaptive applications where graph structure, execution times and data rates may change dynamically. The analysis technique combines symbolic simulation in (max; +) algebra with worst-case resource availability curves. It further enables a tighter performance guarantee by improving the WCRTs of service requests that arrive in the same busy time. Evaluation on real-life application graphs shows that the technique is tens of times faster than the state-of-the-art and enables tighter throughput guarantees, up to a factor of 4, compared to the typical worst-case analysis.

End-to-End Latency Analysis of Dataflow Scenarios Mapped Onto Shared Heterogeneous Resources

The design of embedded wireless and multimedia applications requires temporal analysis to verify if real-time constraints such as throughput and latency are met. This paper presents a design-time analytical approach to derive a conservative upper bound to the maximum end-to-end latency of a streaming application. Existing analytical approaches often assume static application models, which cannot cope with the data-dependent execution of dynamic streaming applications. Consequently, they give overly pessimistic upper bounds. In this paper, we use an expressively richer dataflow model of computation as an application model. The model supports adaptive applications that change their graph structure, execution times, and data rates, depending on their mode of operation, or scenario. We first formalize the latency analysis problem in the presence of dynamically switching scenarios. We characterize each scenario with a compact matrix in (max, +) algebra using a symbolic execution of one graph iteration. The resulting matrices are then composed to derive a bound to the end-to-end latency under a periodic source. Aperiodic sources such as sporadic streams can be analyzed by reduction to a periodic reference. We demonstrate the applicability of the technique with dataflow models from the wireless application domain. Moreover, the method is illustrated with a tradeoff analysis in resource reservation under a throughput constraint. The evaluation shows that the approach has a low runtime, which enables it to be effectively integrated in multiprocessor design flows of streaming applications.

MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis

Heterogeneous Multiprocessor systems-on-chip (HMPSoC) are becoming popular as a means of meeting energy efficiency requirements of modern embedded systems. However, as these HMPSoCs run multimedia applications as well, they also need to meet realtime requirements. Designing HMPSoCs with predictable timing behavior is a key challenge, as the current design methods for these platforms are semi-automated, non-predictable, or support limited heterogeneity. In this demonstration, we present a design framework to rapidly generate and implement predictable HMPSoC designs. It takes the application specifications and the architecture model as input and generates the entire HMPSoC, for FPGA prototyping, that meets the throughput constraints of the application. We also present results of a case study that computes the performance-power tradeoffs of an industrial vision application. A tool-chain targeting the Xilinx Zynq FPGA is also presented.