Shakith Fernando

Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA

Future applications for embedded systems demand chip multiprocessor designs to meet real-time deadlines. The large number of applications in these systems generates an exponential number of use-cases. The key design automation challenges are designing systems for these use-cases and fast exploration of software and hardware implementation alternatives with accurate performance evaluation of these use-cases. These challenges cannot be overcome by current design methodologies which are semiautomated, time consuming, and error prone. In this article, we present a design methodology to generate multiprocessor systems in a systematic and fully automated way for multiple use-cases. Techniques are presented to merge multiple use-cases into one hardware design to minimize cost and design time, making it well suited for fast design-space exploration (DSE) in MPSoC systems. Heuristics to partition use-cases are also presented such that each partition can fit in an FPGA, and all use-cases can be catered for. The proposed methodology is implemented into a tool for Xilinx FPGAs for evaluation. The tool is also made available online for the benefit of the research community and is used to carry out a DSE case study with multiple use-cases of real-life applications: H263 and JPEG decoders. The generation of the entire design takes about 100 ms, and the whole DSE was completed in 45 minutes, including FPGA mapping and synthesis. The heuristics used for use-case partitioning reduce the design-exploration time elevenfold in a case study with mobile-phone applications.

Project-Based Learning in Embedded Systems Education Using an FPGA Platform

With embedded systems becoming ubiquitous, there is a growing need to teach and train engineers to be well-versed in their design and development. The multidisciplinary nature of such systems makes it challenging to give students exposure to and experience in all their facets. This paper proposes a generic architecture, containing multiple processors, that allows easy integration of custom and/or predefined peripherals. The architecture allows students to explore both the hardware and software issues associated with real-time and embedded systems. Furthermore, the architecture can be extended to train students in advanced concepts in embedded multiprocessor systems. This generic architecture has been used for two courses at the National University of Singapore-one on real-time embedded systems and the other emphasizing the hardware aspects of embedded systems. The project in the real-time embedded systems course has students develop a five-a-side soccer system on multiple field-programmable gate array (FPGA) boards using embedded processors. In the embedded hardware design course project, students use an embedded processor-based system to perform decryption of a block encrypted image, accelerated through a custom co-processor. The use of displays gives students a visual/interactive experience and a sense of accomplishment, while reinforcing the theoretical concepts. Both qualitative and quantitative assessment results are presented, showing how students perceived these projects and met the learning objectives.

Multi-Processor System-Level Synthesis for Multiple Applications on Platform FPGA

Multiprocessor systems-on-chip (MPSoC) are being developed in increasing numbers to support the high number of applications running on modern embedded systems. Designing and programming such systems prove to be a major challenge. Most of the current design methodologies rely on creating the design by hand, and are therefore error-prone and time-consuming. This also limits the number of design points that can be explored. While some efforts have been made to automate the flow and raise the abstraction level, these are still limited to single-application designs. In this paper, we present a design methodology to generate and program MPSoC designs in a systematic and automated way for multiple applications. The architecture is automatically inferred from the application specifications, and customized for it. The flow is ideal for fast design space exploration (DSE) in MPSoC systems. We present results of a case study to compute the buffer-throughput trade-offs in real-life applications, H263 and JPEG decoders. The generation of the entire project takes about 100 ms, and the whole DSE was completed in 45 minutes, including the FPGA mapping and synthesis.

MAMPSx: A design framework for rapid synthesis of predictable heterogeneous MPSoCs

Heterogeneous Multiprocessor System-on-Chips (HMPSoC) are becoming popular as a means of meeting energy efficiency requirements of modern embedded systems. However, as these HMPSoCs run multimedia applications as well, they also need to meet real-time requirements. Designing these predictable HMPSoCs is a key challenge, as the current design methods for these platforms are either semi-automated, non-predictable, or have limited heterogeneity. In this paper, we propose a design framework to generate and program HMPSoC designs in a rapid and predictable manner. It takes the application specifications and the architecture model as input and generates the entire HMPSoC, for FPGA prototyping, that meets the throughput constraints. The experimental results show that our framework can provide a conservative bound on the worst-case throughput of the FPGA implementation. We also present results of a case study that computes the area-power trade-offs of an industrial vision application. The entire design space exploration of all configurations was completed in 8 hours. A tool-chain targeting the Xilinx Zynq FPGA is also presented.

Pseudo-random single photon counting for time-resolved optical measurement

We report a new time-resolved optical measurement method which combines single photon counting and the spread spectrum time-resolved optical measurement method. A laser diode modulated with pseudo-random bit sequences replaces the short pulse laser used in conventional time-resolved optical systems, while a single photon detector records the pulse sequence in response to the modulated excitation. Periodic cross-correlation is used to retrieve the impulse response. Feasibility of our approach is validated experimentally. A rise time around 150 picoseconds has been achieved with our prototype. Besides high temporal resolution, the new method also affords other benefits such as high photon counting rate, fast data acquisition, portability, and low cost.

Ultra Storage-Efficient Time Digitizer for Pseudorandom Single Photon Counter Implemented on a Field-Programmable Gate Array

Pseudorandom single photon counting is a novel time-resolved optical measurement method, which is advantageous over convention techniques in terms of data-acquisition speed and system cost. As a critical component of the pseudorandom single photon counter, the photon arriving time digitizer should be storage efficient for a high photon counting rate, while maintaining good time accuracy. We report an ultra storage-efficient time digitizer for a pseudorandom single photon counter in this paper, which is based on the asynchronous serial communication and can store the arriving time of every photon in 1-b memory space. In addition, a novel comb-wave modulator is proposed to achieve the dc balance required for asynchronous serial communication. Our prototype implemented on field-programmable gate arrays provides a time resolution of 400 ps. It can register up to 4.2-Giga photon arriving time tags with 1024 × 32-b memory space.

MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis

Heterogeneous Multiprocessor systems-on-chip (HMPSoC) are becoming popular as a means of meeting energy efficiency requirements of modern embedded systems. However, as these HMPSoCs run multimedia applications as well, they also need to meet realtime requirements. Designing HMPSoCs with predictable timing behavior is a key challenge, as the current design methods for these platforms are semi-automated, non-predictable, or support limited heterogeneity. In this demonstration, we present a design framework to rapidly generate and implement predictable HMPSoC designs. It takes the application specifications and the architecture model as input and generates the entire HMPSoC, for FPGA prototyping, that meets the throughput constraints of the application. We also present results of a case study that computes the performance-power tradeoffs of an industrial vision application. A tool-chain targeting the Xilinx Zynq FPGA is also presented.

Bringing soccer to the field of real-time embedded systems education

With embedded systems penetrating our daily lives, there is a growing need to teach and train engineers who are well-versed in designing and developing such platforms. Owing to multi-disciplinary nature of real-time embedded systems, imparting exposure and experience in all facets of such systems is challenging. While most existing courses use a variety of hands-on projects to this end, they are usually limited to single-processor designs. In this paper, we describe a real-time embedded systems project that is being used at the National University of Singapore. The aim of the project is to develop a 5-a-side soccer system on multiple Xilinx FPGA boards using embedded processors. Besides exposing the students to real-time concepts like scheduling, handling shared resources and priority management, the project also makes them appreciate the constraints in a typical embedded system while still making it a fun experience for them. A minicompetition is organized at the end of the project where all teams compete against each other in a knock-out tournament with 5-minute games where the progress of the game is shown on an attached VGA screen. The approach adopted in the project gives students a sense of accomplishment while reinforcing the theoretical concepts. The project has been successfully run for two terms and a similar idea has been applied in another module on embedded systems.

sFPGA — A scalable switch based FPGA architecture and design methodology

The poor scalability of current mesh-based FPGA interconnection networks is impeding our attempts to build next-generation FPGA of larger logic capacity. A few alternative interconnection network architectures have been proposed for future FPGAs, but they still have several design challenges that need to be addressed. In this paper, we propose sFPGA, a scalable FPGA architecture, which is a hybrid between hierarchical interconnection and network-on-chip. The logic resources in sFPGA are organized into an array of logic tiles. The tiles are connected by a hierarchical network of switches, which route data packets over the network. In addition, we have proposed a design flow for sFPGA which integrates current design flows seamlessly. By doing a case study in our emulation prototype, we have validated our sFPGA design flow.

Design of a high speed pseudo-random bit sequence based time resolved single photon counter on FPGA

Diffuse optical tomography is a rapidly developing imaging technology for biomedical research and clinical studies. A commonly used technique for detecting diffused photons is time correlated single photon counting mechanism, which time stamps the photons while capturing signal. However, time stamping requires an extremely long data acquisition time. Using a spread-spectrum approach, a novel time correlated single photon counting algorithm based on pseudo random bit sequences has been proposed as a solution. This paper describes a FPGA implementation of this pseudo random bit sequence based single photon counter, leveraging the rapid prototyping capabilities of reconfigurable computing. The design consists of a high speed pseudo random number generator and a high speed data reconstruction unit. Furthermore, a demo prototype has been built for experimentation.