Focko Frieling

Design Methodology for a DVB Satellite Receiver ASIC

This contribution describes design methodology and implementation of a single-chip timing and carrier synchronizer and channel decoder for digital video broadcasting over satellite (DVB-S). The device consists of an A /D converter with AGC, timing and carrier synchronizer with matched filter, Viterbi decoder including node synchronization, byte and frame synchronizer, convolutional de-interleaver, Reed Solomon decoder, and a descrambler.The system was designed in accordance with the DVB specifications. It is able to perform Viterbi decoding at data rates up to 56 Mbit /s and to sample the analog input values with up to 88 MHz. The chip allows automatic acquisition of the convolutional code rate and the position of the puncturing mask. The symbol synchronization is performed fully digitally by means of interpolation and controlled decimation. Hence, no external analog clock recovery circuit is needed.For algorithm design, system performance evaluation, co-verification of the building blocks, and functional hardware verification an advanced design methodology and the corresponding tool framework are presented which guarantee both short design time and highly reliable results. The chip has been fabricated in a 0.5 µm CMOS technology with three metal layers. A die photograph is included.

Analysis strategy for internal measurements on VLSI devices

Abstract In the VLSI product development, design as well as process related failures may be regarded as the cause for systematic malfunctions on the chip, concealing additional statistical defects and weaknesses. In an extreme case — as will be reported here — the storage function of a DRAM was crippled by serious faults in the peripheral logic. Consequently no experience was gained with respect to the storage cell area, in which the highest level of integration is achieved. This has very severe consequences for the learning curve, which normally must be very steep due to enormous market pressure. Considering the extreme complexity of todays integrated circuits (submicron regime) this steep condition is however hard to maintain. The present paper outlines an analysis strategy of how these difficulties can be overcome if the conditions are favorable, and thus stay on the learning curve.

An All-Digital Single-Chip Symbol Synchronizer and Channel Decoder for DVB

In this contribution, design process and implementation of a single-chip timing and carrier synchronizer and channel decoder for digital video broadcasting over satellite (DVB-S) is described. The device consists of an A-to-D-converter with AGC, timing and carrier synchronizer including matched filter, Viterbi decoder including node synchronization, byte and frame synchronizer, convolutional de-interleaver, Reed Solomon decoder, and a descrambler. The system was designed in accordance with the DVB specifications. It is able to perform Viterbi decoding at data rates up to 56 Mbit/s and to sample the analog input values with up to 88 MHz. The chip allows automatic acquisition of the convolutional code rate and the position of the puncturing mask. The synchronization to the variable sample rates is performed fully digital by means of interpolation and controlled decimation. Hence, no external analog clock recovery circuit is needed. For algorithm design, system performance evaluation, and co-verification of the building blocks an advanced design methodology was used. This guarantees both short design time and high reliability. The chip has been fabricated in a 0.5 Am CMOS technology with three metal layers. A die photograph is presented.