Forrest Brewer

Clock skew optimization for ground bounce control

High speed synchronous digital systems require large switching currents to facilitate rapid signal transitions. These large currents create voltage drops on the power distribution network and necessitate expensive chip packaging with a large number of supply pins. In this paper we propose a novel technique to reduce the dynamic transient current drawn from the supply pins. Our approach is based on sub-dividing the synchronous clocking into multiple sub-clocks with relative skew. This spreads the computation across the entire clock cycle instead of largely occurring at the beginning. Timing constraints must also be obeyed, so that no races or timing errors are introduced. We propose an exact algorithm based on integer linear programming to solve this problem. We have used our method in the design of a 5 GHz ECL encoder chip to achieve a factor of two reduction in ground bounce, as shown by HSPICE simulations. We also obtained order-of-magnitude improvements in ground bounce on benchmarks laid our in submicron CMOS technology. The approach potentially leads to significant reductions in packaging costs.

Implementation of an efficient parallel BDD package

Large BDD applications push completing resources to their limits. One solution to overcoming resource limitations is to distribute the BDD data structure across multiple networked workstations. This paper presents an efficient parallel BDD package for a distributed environment such as a network of workstations (NOW) or a distributed memory parallel computer. The implementation exploits a number of different forms of parallelism that can be found in depth-first algorithms. Significant effort is made to limit the communication overhead, including a two-level distributed hash table and an uncomputed cache. The package simultaneously executes multiple threads of computation on a distributed BDD.

Clairvoyant: a synthesis system for production-based specification

This paper describes a new high-level synthesis system based on the hierarchical production based specification (PBS). Advantages of this form of specification are that the designer does not describe the control flow in terms of explicit states or control variables, and that the designer does not describe a particular form of implementation. The production-based specification also separates the specification of the control aspects and data-flow aspects of the design. The control is implicitly described via the production hierarchy, while the data-flow is described as action computations. This approach is a hardware analog of popular software engineering techniques. The Clairvoyant system automatically constructs a controlling machine from the PBS and this process is not impacted by the possibly exponentially larger deterministic state space of the designs. The encodings generated by the constructions compare favorably to encodings derived using graph-based state encoding techniques in terms of logic complexity and logic depth. These construction techniques utilize recent advances in BDD techniques. >

Chippe: a system for constraint driven behavioral synthesis

The Chippe system for constrained behavioural architecture synthesis uses a novel closed-loop design iteration technique in which the present state of the design is analyzed with respect to the goals and then modified for the next iteration. In this way the design state is iteratively driven towards meeting the global constraints imposed by the designer. The design synthesis is performed by a set of algorithmic tools specially constructed to permit the imposition of a wide variety of local constraints, and by a rule-based system which makes design analysis and modification decisions to set these local constraints. Key to these decisions is a design evaluator which examines the present state of the design and interactively reports its findings to the rule-based system. The closed-loop iteration strategy, the interaction between the rule base and the tools, and the evaluation performed to support the design decisions are detailed. Also presented are results from sample designs, including designs for the TMS320 digital signal processor chip. >

A new symbolic technique for control-dependent scheduling

This paper describes an exact symbolic formulation of control-dependent, resource-constrained scheduling. The technique provides a closed-form solution set in which all satisfying schedules are encapsulated in a compressed OBDD-based representation. This solution format greatly increases the flexibility of the synthesis task by enabling incremental incorporation of additional constraints and by supporting solution space exploration without the need for rescheduling. The technique provides a systematic treatment of speculative operation execution in arbitrary forward-branching control/data paths. An iterative construction method is presented along with benchmark results. The experiments demonstrate the ability of the proposed technique to efficiently exploit parallelism not explicitly specified in the input description.

DISC: dynamic instruction stream computer

The Dynamic Instruction Stream Computer is a novel computer architecture which addresses many of the problems present in real-time systems. The DISC operates by allowing multiple instruction streams (ISs), representing different processes to run concurrently by instruction interleaving on the pipeline. Also, the throughput of the DISC can be partitioned in any way between the multiple ISs. Conventional architectures are more concerned with overall performance and throughput than with real-time response. In other words, they optimize the system to the functions that are more heavily used without regard to responsiveness to individual requests. Applications abound where a high degree of responsiveness is required, without too much sacrifice of overall efficiency. This is particularly true in real-time control applications where it is important to optimize the critical loops and respond promptly to interrupts. DISC addresses this problem by dynamically partitioning the processor throughput between multiple instruction streams based upon requirement demands. In this way different tasks and interrupt priorities can be assigned to guarantee their deadlines.

Buffer delay change in the presence of power and ground noise

Variations of power and ground levels affect very large scale integration circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the presence of uncorrelated power and ground noise. In this paper, we analyze the effect of such noise-on-signal propagation through a buffer and present simple, closed-form formulas to estimate the corresponding change of delay. The model captures both positive (slowdown) and negative (speedup) delay changes. It is consistent with short-channel MOSFET behavior, including carrier velocity saturation effects. An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply-level-induced jitter characteristics. The expressions can be used in any existing circuit performance optimization design flow or can be combined into any delay calculations as a correction factor.

Coping with buffer delay change due to power and ground noise

Variation of power and ground levels affect VLSI circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the presence of uncorrelated power and ground noise. In this paper, we analyze the effect of such noise on signal propagation through a buffer and present simple, closed-form formulas to estimate the corresponding change of delay. The model captures both positive (slowdown) and negative (speedup) delay changes. It is consistent with short-channel MOSFET behavior, including carrier velocity saturation effects. An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply level-induced jitter characteristics.

High-level Symbolic Construction Techniques for High Performance Sequential Synthesis

Techniques for constructing synchronous sequential machines with associated data paths from an input format consisting of high-level non-deterministic productions are described. These construction techniques rely on recent work in symbolic Boolean representation and manipulation to produce an intermediate machine representation that is not impacted by state explosion.

Efficient encoding for exact symbolic automata-based scheduling

This paper presents an efficient encoding and automaton construction which improves performance of automata-based scheduling techniques. The encoding preserves knowledge of what operations occurred previously but excludes when they occurred, allowing greater sharing among scheduling traces. The technique inherits all of the features of BDD-based control dominated scheduling including systematic speculation. Without conventional pruning, all schedules for several large samples are quickly constructed.