Merritt Miller

Formal verification of analog circuit parameters across variation utilizing SAT

A fast technique for proving steady-state analog circuit operation constraints is described. Based on SAT, the technique is applicable to practical circuit design and modeling scenarios as it does not require algebraic device models. Despite the complexity of representing accurate transistor I/V characteristics, run-time and problem scaling behavior is excellent.

5 Gbps Radiation-Hardened Low-Power Pulse Serial Link

Presented is a high-speed, radiation hardened by design, physical layer data link. The 5 Gbps link is implemented in an 130 nm process occupying relatively small area and having low power (60 mW total). The data rate, radiation hardness, and power consumption are all enabled by asynchronous circuits utilizing a pulse-base wire encoding that, in combination, dramatically simplifies data recovery while increasing timing tolerances in both transmitter and receiver designs. This means that neither the transmitter nor the receiver uses a high-speed clock, instead, small asynchronous state machines handle the transmit and receive functions as well as serialization and deserialization. These small structures contribute to radiation hardness by allowing for efficient modular redundancy at high speeds. The design is also hardened for long environment lifetime (very high total irritated dose of greater than 300MRad Si). This paper specifically addresses the design implementation trade-offs and high-speed design methodology for the link with simulation results as well as preliminary test data.

Multi-gigabit low-power radiation-tolerant data links and improved data motion in trackers

We present a set of links based on data-transmission IP in 130nm designed for rapid integration into ASIC designs. These links are designed for use in very high radiation environments as occur in high energy physics experiments. The designs are additionally low power and small area, easing integration with other electronic systems. These links are well suited to use in tracking detectors. Trackers, due to their close proximity to the collision, are subject to very high levels of radiation, and hence require such radiation hardened electronics. The portfolio of radiation hardened data transmission blocks consists of a 1Gbps serializer/deserializer with a very low power consumption ~1mW for each. A differential transmitter and differential receiver rated at 3GHz, both designed to be much faster than needed, as insurance against radiation damage. Finally, the impact of a prototype low-latency, low-power ( < 60mW total link power) 5Gbps link is considered. Case analysis of the impacts of using lower powered, higher speed blocks in hypothetical trackers is studied, showing power improvements relative to alternative technologies.

Pulse Ring Oscillator Tuning via Pulse Dynamics

This paper presents a practical method for improving timing uncertainty due to thermal noise in a ring oscillator. The methodology utilizes delay elements with non-linear behavior dependent on event separation, the period between successive events. Pulse logic gates are shown to have delay-separation dynamics which can impact the statistics of subsequent events in the oscillators. The slope of the delay-separation is shown to linearly improve the uncertainty in these oscillators. Multiple pulses in a ring is also shown to linearly improve the timing uncertainty.

Connectivity Effects on Energy and Area for Neuromorphic System with High Speed Asynchronous Pulse Mode Links

Hardware neuromorphic systems are challenged to achieve biologically realistic levels of interconnectivity. When building a physical implementation of a neural net, the properties of the media immediately impose limits on the number of interconnects and available timing options. The design of any system must consider the energy and area costs associated with the physical layout of neuron core connectivity, rst, by accepting the wiring limits imposed by Rents rule and second, by understanding the temporal overhead introduced by routing. The presented results show the energyarea trade-o for a model of a neuromorphic system with event driven interconnections. The low area overhead of the asynchronous pulse-mode links create an attractive opportunity for a digital neuromorphic system with a connectivity model closer to the existing software models of neural nets.

Asynchronous High Speed Serial Links Analysis using Integrated Charge for Event Detection

We present a metric for event detection, targeted for the analysis of CMOS asynchronous serial data links. Our metric is used to analyze signaling strategies that allow for coincident or nearly coincident detection of both data and event timing. The metric predicts that the CMOS link signaling mechanism has substantial implicit dispersion and intersymbol interference [ISI] tolerance when compared to conventionally timed links. In fact, it predicts correct link operation in situations where eye-diagram techniques predict link failure. Practical operation margins and metrics are described and evaluated for PCB and cabling solutions suggesting 10+ Gb/s low-power asynchronous links could be implemented in CMOS 130nm technology.

Impolite High Speed Interfaces with Asynchronous Pulse Logic

We present a design solution that allows design of higher-than-core rate operation with techniques that avoid PLL/DLL blocks to provide higher speed timing. Many modern integrated circuits (ICs) have high speed interfaces which operate at higher cycle rates than the core of the IC. As a result of the higher-than-core rate, these interfaces are not directly representable in the core sequential logic. Asynchronous pulse logic offers an alternative design method for high speed interfaces with similar performance, simpler circuitry and without resorting to high-power logic cells such as emitter coupled logic. Formal and practical considerations for constructing high-speed interfaces are described. Gate designs and timing information for example cases are presented. These cases suggest that 80% improvements on rate compared traditional clocked logic are possible.

Design and analysis of high performance pulse ring VCO

This paper presents a low phase noise, low power, wide tuning range, small area pulse ring oscillator fabricated in inexpensive 130nm CMOS technology. The ring uses very non-linear Pulse gates instead of conventional inverters as buffers substantially reducing the impulse sensitivity function (ISF) and thus the phase noise. The timing signal is rising-edge and ground referenced, allowing the supply to be used as control voltage. 6dB phase noise improvement is projected in ISF based phase noise simulation over a same frequency ring oscillator. Fabricated ring oscillators show a phase noise of −97.46 dBC/Hz at 1MHz offset for 1.889GHz oscillator at 2.94mW power consumption and −95.13 dBC/Hz at 1MHz offset for 897MHz oscillator at 617uW power consumption. The oscillators have a tuning range of 513MHz to 2.64GHz. Figure of merit of the design shows a better performance than any other non phase locked voltage controlled ring oscillator.

Radiation-tolerant IP-cores for 2Gbps serial links for the data readout in future LHC experiments

The increase of luminosity foreseen for the future upgrades of the Large Hadron Collider at CERN will require the complete redesign of the Front-End electronics in all the experiments. One of the goals of the RD53 collaboration is the development of a full set of radiation-tolerant IP-cores in view of the design in 2016 of the first prototype of the new Front-End circuit for the pixel detectors of the ATLAS and CMS experiments. In this framework we designed radiation-tolerant 2Gbps Serializer and Deserializer modules and 3GHz differential SLVS Driver and Receiver devices in a commercial 65nm CMOS technology. IP-cores will be described and results of tests on first prototypes will be presented, including results of irradiation tests with heavy ions.

5GB/s radiation hard low power point to point serial link

The presented system is a high-speed radiation hardened by design link technology. The link operates at 5Gbps, and occupies a very small area (50μ×200μ+pad for each TX and RX) in its 130nm implementation. The on the wire encoding is in the form of pulses, dramatically simplifying the data recovery process, allowing flexibility in the transmitter and receiver design. Neither the transmitter nor the receiver uses a high-speed clock, instead small state machines are used to handle the transmit and receive functions.