Fotis Plessas

A study of superharmonic injection locking in multiband frequency dividers

A superharmonic voltage-controlled injection-locked frequency divider, implemented using a modified Colpitts oscillator operating at 2.5, 5 and 10 GHz and a cross-coupled LC oscillator operating at 1.25, 2.5 and 5 GHz, is demonstrated. The proposed triple-band operation is achieved by employing a novel technique that uses pin-diodes and negative power supply. The discrete dividers, built with low noise hetero-junction FETs and high-frequency SiGe BJTs, are described theoretically while their functionality is proven experimentally. Additionally, a short phase noise analysis, which is missing in the literature, is given. Phase noise, frequency range of operation, and locking range measurement results are presented. Finally, post-layout simulation results of a 5 GHz fully differential injection-locked frequency divider, implemented in a 0.25µm SiGe process are provided. Copyright

A 5-GHz Subharmonic Injection-Locked Oscillator and Self-Oscillating Mixer

This paper presents a multifunctional circuit realizing the functions of oscillation, mixing, amplification, and frequency multiplication at 5 GHz. A theoretical and experimental description of the circuit is given. The proposed circuit, which combines both the injection-locking and mixing processes, uses only one port where both the RF/intermediate frequency signal and the injection signal (IS) are applied. The IS, which is used to stabilize the oscillation, is at a subharmonic of the oscillation frequency (omegaosc/4) having a power level as low as -50 dBm. Calculations of the phase noise and measurements of the mixing properties are reported which indicate a noise improvement, and a high up-conversion gain. The implementation of the circuit exhibits an up-conversion gain of 14 dB, a phase noise of -110 dBc/Hz at 100-kHz offset, a dB of -15 dBm, a third-order intercept point of -2 dBm, and a power consumption of 35 mW. Calculated and measured results are in good agreement for all cases, emphasizing the relevance of the proposed circuit.

A sub-1V supply CMOS voltage reference generator

An integrated sub-1V voltage reference generator, designed in standard 90-nm CMOS technology, is presented in this paper. The proposed voltage reference circuit consists of a conventional bandgap core based on the use of p-n-p substrate vertical bipolar devices and a voltage-to-current converter. The former produces a current with a positive temperature coefficient (TC), whereas the latter translates the emitter-base voltage of the core p-n-p bipolar device to a current with a negative TC. The circuit includes two operational amplifiers with a rail-to-rail output stage for enabling stable and robust operation overall process and supply voltage variations while it employs a total resistance of less than 600 K Ω. Detailed analysis is presented to demonstrate that the proposed circuit technique enables die area reduction. The presented voltage reference generator exhibits a PSRR of 52.78 dB and a TC of 23.66ppm/∘C in the range of − 40 and 125∘C at the typical corner case at 1 V. The output reference voltage of 510 mV achieves a total absolute variation of ± 3.3% overall process and supply voltage variations and a total standard deviation, σ, of 4.5 mV, respectively, in the temperature range of − 36 and 125∘C. Copyright

Locking techniques for RF oscillators at 5-6 GHz frequency range

This work aims at analyzing three different techniques for synchronizing RF oscillators. These techniques are Injection Locking (ILO), Phase Locked Loop (PLL) and Injection Locked Phase Locked Loop (ILPLL). ILPLL, which is a combination of PLL and ILO, has superior noise performance -compared to all the rest- at medium frequency offsets and the same noise performance at low and high offsets. Furthermore, the ILPLL has better locking range and lower phase noise than the ILO for phase-shifts close to /spl plusmn/90/spl deg/. In this work we present two different approaches for the study of the performance of the ILPLL, which as we show, produce equivalent results concerning the noise. A common gate VCO was used and the injected signal was the same for comparison reasons.

A linear, ultra wideband, low-power, 2.1–5 GHz, VCO

A linear, Ultra Wideband, low-power VCO, suitable for UWB-FM applications is proposed, forming the main part of a UWB-FM transmitter. The VCO is designed in TSMC 90thinspacenm digital CMOS process and includes a Source-Coupled Multivibrator, used as current-controlled oscillator (CCO) which generates output frequencies between 2.1 and 5 GHz and a voltage-to-current (V-to-I) converter which translates the VCO input voltage modulation signal to current. Two single-ended inverter buffers are employed to drive either a differential or a single-ended UWB antenna. The presented VCO is designed for 1 V power supply and exhibits a linear tuning range of 2.1–5 GHz, a differential output power of −7.83 dBm±0.78 dB and low power consumption of 8.26 mW, including the output buffers, at the maximum oscillation frequency. It is optimized for a very high ratio of tuning range (81.69%) over power consumption equal to 9.95 dB. The desired frequency band of 3.1–5 GHz for UWB-FM applications is covered for the entire industrial temperature range (−40 to 125∘C). Copyright

Phase noise characterization of subharmonic injection locked oscillators

SUMMARY In this work we present a detailed study of the phase noise of subharmonic injection locked oscillators (s-ILOs). A new simple and efficient model has been presented for accurately predicting the phase noise of a microwave s-ILO. The validity of the analytical technique is verified with measurement results obtained from a 5-GHz fully differential Colpitts-based s-ILO. The results showed that a phase noise improvement of 12dB at 1kHz offset frequency compared to the free-running case can be achieved, whereas the power consumption is 21mW. Copyright 2010 John Wiley & Sons, Ltd.

A Subharmonic Injection-Locked Self-Oscillating Mixer

A subharmonic injection-locked self-oscillating mixer (s-ILSOM) at 1 GHz is reported in this paper. The proposed circuit which combines both injection-locking and mixing functions is described theoretically and experimentally. In contrast to previously reported works, only one input port is required for both the RF/IF signal and the injection signal. Furthermore, the injection signal which is used to stabilize the oscillation is at a subharmonic of the oscillation frequency (fLO/4), with a power level as low as -20 dBm. Phase noise calculations and mixing characteristics are reported, indicating a noise improvement, and a high up-conversion gain for both fundamental and harmonic mixing. The circuit is implemented, using a GaAs FET, exhibiting an up-conversion gain of 13 dB, a phase noise of -93 dBc/Hz at 100 KHz offset, a P1dB of -18 dBm, an IP3 of -5 dBm, and a power consumption of 24 mW.

A 5-GHz, variable gain, SiGe low noise amplifier

A bipolar low noise amplifier (LNA) is described in this work. The IC contains the LNA core, an externally programmed bias network, a voltage divider, an LC tank and inductors to set the input impedance. The externally programmed bias network allows the user to select the bias current in an adaptive manner, depending upon the requirements of the individual system. (Low NF, high gain, low consumption etc). The chip can be powered down by sending an appropriate bit stream to the bias network. The tuned amplifier using a parallel LC network provides selective amplification and lower power consumption. The produced gain is 15 dB while the NF is 2.1 dB for moderate power consumption. The IIP3 is -7 dB and the P/sub 1dB/ is -17 dB. The power consumption from a single 5-V supply is 3.4 mA for the low gain mode and 13 mA for the high gain mode.

A 5‐Gbps USB3.0 transmitter and receiver linear equalizer

Summary A USB3.0 compatible transmitter and the linear equalizer of the corresponding receiver are presented in this paper. The architecture and circuit design techniques used to meet the strict requirements of the overall link design are explored. Output voltage amplitude and de-emphasis levels are programmable, whereas the output impedance is calibrated to 50Ω. A programmable receiver equalizer is also presented with its main purpose being to compensate for the channel losses; this is employed together with a DC offset compensation scheme. The 6.25-GHz equalizer provides a 10 dB overall gain equalization and 5.5-dB peaking at the maximum gain setting. Designed using a mature and well established 65 nm complementary metal oxide semiconductor process, the layout area is 400 µm × 210 µm for the transmitter core, and 140 µm × 70 µm for the equalizer core. The power consumption is 55 and 4 mW, respectively, from a 1.2 V supply at a data rate of 5 Gbps. The target application for such high-speed blocks is to implement the critical part of the physical layer that defines the signaling technology of SuperSpeed USB3 PHY. However, identical iterations of the circuitry discussed can be used for similar high-speed applications like the PCI express (PCIe). Copyright

A variable gain wideband CMOS low-noise amplifier for 75 MHz–3 GHz wireless receivers

A wideband CMOS variable gain low noise amplifier suitable for multi-standard radio applications between 75 MHz and 3 GHz is presented. Wideband matching to 50 Ohm (single ended) is achieved using a common-drain feedback stage whereas variable gain is realized using a resistive attenuator. The circuit has been designed in a 65 nm CMOS process and achieves 22 dB maximum gain, 29 dB gain range, 3.3 dB noise figure, and an IIP3 higher than -4 dBm.