John Kikidis

Investigation of 10-Gb/s RSOA-Based Upstream Transmission in WDM-PONs Utilizing Optical Filtering and Electronic Equalization

Enhanced upstream transmission at 10 Gb/s using a low-bandwidth reflective semiconductor optical amplifier is demonstrated and discussed for extended wavelength- division-multiplexing passive-optical-network applications. Significant improvement in terms of transmission performance is achieved with the use of electronic equalization and optimum filter offset placed at the receiver (optical line terminal) end only. According to filtering detuning, an analytical discussion is presented, explaining the bandwidth enhancement achieved with the proposed technique. The experimental studies consider the benefits of the electronic feed-forward and decision-feedback equalization as well as the required optimum offset optical filtering characteristics.

10 Gb/s full-duplex bidirectional transmission with RSOA-based ONU using detuned optical filtering and decision feedback equalization

Full-duplex bidirectional transmission at 10 Gb/s is demonstrated for extended wavelength division multiplexed passive optical network (WDM-PON) applications, achieving transmission distances up to 25 km of standard single mode fiber (SSMF) when using a low-bandwidth (approximately 1.2 GHz) reflective semiconductor optical amplifier (RSOA) for signal re-modulation at the optical network unit (ONU). The system is assisted by optimum offset filtering at the optical line terminal (OLT)-receiver and the performance is further improved with the use of decision-feedback equalization (DFE). Chromatic dispersion (CD) and Rayleigh Backscattering (RB) effects are considered and analyzed.

Design Characteristics for a Full-Duplex IM/IM Bidirectional Transmission at 10 Gb/s Using Low Bandwidth RSOA

In this paper, the optimum design characteristics and the transmission performance limits of an intensity modulation full-duplex bidirectional transmission system at 10 Gb/s are experimentally studied and presented for application in next-generation-extended wavelength-division-multiplexed passive optical networks. A low-bandwidth (~1.2 GHz) reflective semiconductor optical amplifier (RSOA) is utilized at the optical network unit (ONU) site of the system. Its remodulation properties and performance are examined for both continuous wave and modulated downstream signal, stemming from the optical line terminal (OLT). The techniques adopted to optimize performance are: 1) the use of detuned optical filtering at the OLT receiver that takes advantage of the RSOA chirp and 2) the use of decision feedback equalization (DFE). The extinction ratio of the downstream signal and the driving operation point of the RSOA are examined experimentally in order to find the optimum conditions for the bidirectional transmission. Moreover, the impact of patterning effects in the performance of the system is evaluated. Finally, the additional performance improvement that is achieved with the use of DFE technique is shown.

Performance Improvement of Low-Cost 2.5-Gb/s Rated DML Sources Operated at 10 Gb/s

The transmission performance improvement of low-cost conventional directly modulated laser (DML) sources, fabricated for operation at 2.5 Gb/s but modulated at 10 Gb/s is presented and experimentally demonstrated. Performance improvement is achieved by electronic feed-forward and decision-feedback equalization as well as offset optical filtering at the receiver end. Experimental studies consider both transient and adiabatic chirp dominated DML sources. The transmission improvement is evaluated in terms of required optical signal-to-noise ratio (OSNR) for bit-error-rate values of 10-9 versus transmission length over uncompensated links of standard single-mode fiber (SSMF). Additionally, the optimum filter position is examined in combination with equalization and in terms of OSNR versus detuning from the center wavelength.

An ultra low area asynchronous combo 4/8/12-bit/quaternary A/D converter based on integer division

An asynchronous A/D Converter architecture based on a binary tree structure is presented in this paper. Two alternative design strategies are presented that lead either to a high mismatch immunity ADC that requires a light calibration logic (area: 0.123mm^2, power: 72mW) or a faster, tinier and even lower power ADC (area: 0.21mm^2, power: 25mW) with lower mismatch immunity that needs a slightly more complicated calibration logic. Both alternative ADC design strategies require at least one or two orders of magnitude lower area than any known approach and a remarkable low power consumption without sacrificing speed. The designed A/D Converter can operate with a configurable resolution of either 4, 8, or 12-bits. Moreover, 6 quaternary digits or three 16-level outputs are also available from the intermediate nodes of the binary tree, for applications that require multi-valued communication lines. Simulation results prove that the peak conversion rate of the high mismatch immunity A/D design alternative exceeds 300, 230 and 225MS/s for 4, 8 and 12-bit resolution, respectively, while the peak conversion rate of the faster design alternative is higher than 500, 440 and 420MS/s for 4, 8 and 12-bit resolution, respectively. An appropriate sample/hold and voltage to current conversion architecture has been developed along with an intelligent output latching technique that improve the achieved signal to noise and distortion ratio by up to 7dB. Moreover, an appropriate calibration method that extends the temperature operating range and compensates for the component mismatches is presented. The ultra low area and power consumption of the developed ADC architecture favours its employment in sensor networks while these features make its use attractive as a building block in time interleaved parallel ADCs for the achievement of ultra high speed conversion.

A sub-1V supply CMOS voltage reference generator

An integrated sub-1V voltage reference generator, designed in standard 90-nm CMOS technology, is presented in this paper. The proposed voltage reference circuit consists of a conventional bandgap core based on the use of p-n-p substrate vertical bipolar devices and a voltage-to-current converter. The former produces a current with a positive temperature coefficient (TC), whereas the latter translates the emitter-base voltage of the core p-n-p bipolar device to a current with a negative TC. The circuit includes two operational amplifiers with a rail-to-rail output stage for enabling stable and robust operation overall process and supply voltage variations while it employs a total resistance of less than 600 K Ω. Detailed analysis is presented to demonstrate that the proposed circuit technique enables die area reduction. The presented voltage reference generator exhibits a PSRR of 52.78 dB and a TC of 23.66ppm/∘C in the range of − 40 and 125∘C at the typical corner case at 1 V. The output reference voltage of 510 mV achieves a total absolute variation of ± 3.3% overall process and supply voltage variations and a total standard deviation, σ, of 4.5 mV, respectively, in the temperature range of − 36 and 125∘C. Copyright

Next generation millimeter wave backhaul radio: Overall system design for GbE 60GHz PtP wireless radio of high CMOS integration

In this paper we present the implementation of an experimental FDD, QPSK, millimeter-wave radio modem (57–64 GHz) for Point to Point (PtP) wireless backhaul applications. The transceiver supports GbE targeting a two-chip solution plus the antenna subsystem, aiming at highly integrated functions in 90nm CMOS technology, for a range of more than 1km. Achieving these levels of overall integration and silicon implementation requires many technological challenges and innovative design approaches. Furthermore, it allows for drastic changes of relevant cost factors enabling the wireless backhaul deployment for broadband services. The present paper is an outcome of the NexGenMiliwave project aiming to prove that it is possible to provide integrated solutions in silicon, based on demanding high frequency PtP requirements and significantly reduce the cost of the relevant backhaul network deployment.

Upstream transmission in WDM PONs at 10Gbps using low bandwidth RSOAs assisted with optical filtering and electronic equalization

Upstream transmission at 10 Gbps over extended access fibre links is demonstrated using a low-bandwidth RSOA assisted by electronic equalization and optimum filter offset at the receiver (OLT) end.

Analogue current quantizer architectures for implementing integer division-like functions

An analogue current quantization circuit that can implement the integer division by a constant number, the integer floor function, and a function generator with a parametric ladder-like output is presented in this paper. These functions can be exploited in Analogue-to-Digital Converters (ADCs), fuzzy logic and neural networks as well as in signal processing units. Various architecture alternatives are presented which achieve different integer division resolution ranging from 1:2 to 1:65536 or more. High speed and low voltage supply are achieved in ADCs that are based on this divider due to the usage of current mode techniques. Nevertheless, the most important advantages of the presented architectures are the very low power consumption and die area that they require.

Calibration Method for a CMOS 0.06mm^2 150MS/s 8-bit ADC

An ultra low area 8-bit Analog-to-Digital Converter (ADC) has been designed achieving a 150MS/s sampling rate and dissipating 34mW power. It is based on integer division circuits that are arranged in a binary tree structure. We emphasize on the digital calibration method of such an ADC in order to extend its operational temperature range and correct the effect of mismatch and process variations. The calibration is achieved by controlling the voltage supply of the root divider and the amplification and offset correction of the residue that is produced by this divider.