Francesco Menichelli

MPARM: Exploring the Multi-Processor SoC Design Space with SystemC

Technology is making the integration of a large number of processors on the same silicon die technically feasible. These multi-processor systems-on-chip (MP-SoC) can provide a high degree of flexibility and represent the most efficient architectural solution for supporting multimedia applications, characterized by the request for highly parallel computation. As a consequence, tools for the simulation of these systems are needed for the design stage, with the distinctive requirement of simulation speed, accuracy and capability to support design space exploration. We developed a complete simulation platform for a MP-SoC called MP-ARM, based on SystemC as modelling and simulation environment, and including models for processors, the AMBA bus compliant communication architecture, memory models and support for parallel programming. A fully operating linux version for embedded systems has been ported on this platform, and a cross-toolchain has been developed as well. Our MP simulation environment turns out to be a powerful tool for the MP-SOC design stage. As an example thereof, we use our tool to evaluate the impact on system performance of architectural parameters and of bus arbitration policies, showing that the effectiveness of a particular system configuration strongly depends on the application domain and the generated traffic profile.

A post-compiler approach to scratchpad mapping of code

ScratchPad Memories (SPMs) are commonly used in embedded systems because they are more energy-efficient than caches and enable tighter application control on the memory hierarchy. Optimally mapping code and data to SPMs is, however, still a challenge. This paper proposes an optimal scratchpad mapping approach for code segments, which has the distinctive characteristic of working directly on application binaries, thus requiring no access to either the compiler or the application source code - a clear advantage for legacy or proprietary, IP-protected applications.The mapping problem is solved by means of a Dynamic Programming algorithm applied to the execution traces of the target application. The algorithm is able to find the optimal set of instructions blocks to be moved into a dedicated SPM, either minimizing energy consumption or execution times. A patching tool, which can use the output of the optimal mapper, modifies the binary of the application and moves the relevant portions of its code segments to memory locations inside of the SPM.

A class of code compression schemes for reducing power consumption in embedded microprocessor systems

Compression of executable code in embedded microprocessor systems, used in the past mainly to reduce the memory footprint of embedded software, is gaining interest for the potential reduction in memory bus traffic and power consumption. We propose three new schemes for code compression, based on the concepts of static (using the static representation of the executable) and dynamic (using program execution traces) entropy and compare them with a state-of-the-art compression scheme, IBMs CodePack. The proposed schemes are competitive with CodePack for static footprint compression and achieve superior results for bus traffic and energy reduction. Another interesting outcome is that static compression is not directly related to bus traffic reduction, yet there is a trade off between static compression and dynamic compression, i.e., traffic reduction.

Side channel analysis resistant design flow

The threat of side-channel attacks (SCA) is of crucial importance when designing systems with cryptographic hardware or software. The FP6-funded project SCARD enhances the typical micro-chip design flow in order to provide a means for designing side-channel resistant circuits and systems. Appropriate SCA-simulation tools and SCA analysis for the designer of secure systems are part of the project goals. We consider these enhancements for traditional design flows of micro-chips as necessary in order to enable the design for the next generation of secure and dependable devices. SCARD is in its final phase, the final result a SCARD chip designed by using the developed design flow is currently implemented

High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips

The design flow of a digital cryptographic device must take into account the evaluation of its security against attacks based on side channels observation. The adoption of high level countermeasures, as well as the verification of the feasibility of new attacks, presently require the execution of time-consuming physical measurements on the prototype product or the simulation at a low abstraction level. Starting from these assumptions, we developed an exploration approach centered on high level simulation, in order to evaluate the actual implementation of a cryptographic algorithm, being it software or hardware based. The simulation is performed within a unified tool based on SystemC, that can model a software implementation running on a microprocessor-based architecture or a dedicated hardware implementation as well as mixed software-hardware implementations with cycle-accurate resolution. Here we describe the tool and provide a large set of design explorations and characterizations based on actual implementations of the AES cryptographic algorithm, demonstrating how the execution of a large set of experiments allowed by the fast simulation engine can lead to important improvements in the knowledge and the identification of the weaknesses in cryptographic algorithm implementations.

Static Minimization of Total Energy Consumption in Memory Subsystem for Scratchpad-Based Systems-on-Chips

In VLSI systems-on-chips (SoC), leakage is expected to override 50% of the total power consumption, and the memory sub-system can be responsible for up to 75% of the power. Scratch-pad memories (SPM) are a proven alternative to cache memories in power-aware SoCs. Optimal SPM mapping has already been investigated for dynamic power reduction in the main memory and for leakage reduction in the SPM itself. This paper addresses the problem of global energy optimization (i.e., active + leakage) in the whole memory sub-system of an SPM-based SoC. We focus on SPMs dedicated to instructions and constant data. We present the technology-level foundation, the mathematical problem formulation, its solution as an integer-linear-programming (ILP) problem, the implemented design flow, and the power reduction results referring to standard benchmarks and ITRS technology data.

Testing power-analysis attack susceptibility in register-transfer level designs

The susceptibility of cryptographic devices to attacks based on power analysis can be both significantly and efficiently tested at early design steps. The results from a real case application show the advantages of the approach.

TikTak: A Scalable Simulator of Wireless Sensor Networks Including Hardware/Software Interaction

We present a simulation framework for wireless sensor networks developed to allow the design exploration and the complete microprocessor-instruction-level debug of network formation, data congestion, nodes interaction, all in one simulation environment. A specifically innovative feature is the co-emulation of selected nodes at clock-cycle-accurate hardware processing level, allowing code debug and exact execution latency evaluation (considering both protocol stack and application), together with other nodes at abstract protocol level, meeting a designer’s needs of simulation speed, scalability and reliability. The simulator is centered on the Zigbee protocol and can be retargeted for different node micro-architectures.

Delay-Tolerant, Low-Power Protocols for Large Security-Critical Wireless Sensor Networks

This paper reports the analysis, implementation, and experimental testing of a delay-tolerant and energy-aware protocol for a wireless sensor node, oriented to security applications. The solution proposed takes advantages from different domains considering as a guideline the low power consumption and facing the problems of seamless and lossy connectivity offered by the wireless medium along with very limited resources offered by a wireless network node. The paper is organized as follows: first we give an overview on delay-tolerant wireless sensor networking (DTN); then we perform a simulation-based comparative analysis of state-of-the-art DTN approaches and illustrate the improvement offered by the proposed protocol; finally we present experimental data gathered from the implementation of the proposed protocol on a proprietary hardware node.

A simulation-based power-aware architecture exploration of a multiprocessor system-on-chip design

We present the design exploration of a system-on-chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of an ad-hoc C++ simulation environment, integrating power models for CPUs, memories and buses used in the design and incorporating software profiling capabilities. The architecture is based on two ARM microprocessors, an AMBA bus and a local bus, DMA unit and other peripherals. Software mapping on the processor has been based on the power/performance profiling results.