Antonio Mastrandrea

Logic Drivers: A Propagation Delay Modeling Paradigm for Statistical Simulation of Standard Cell Designs

In nanoscale digital CMOS IC design, the large technology parameter variations have boosted the interest in statistical performance analysis. As the huge execution time of SPICE-based transistor-level Monte Carlo analysis is impractical for complex designs, there is a need for making accurate Monte Carlo analysis feasible through fast logic-level simulators. This paper presents a new, general logic model of digital CMOS cells featuring technology variation aware timing, and its prototype implementation in a standard hardware-description-language environment. The application of the approach to typical standard cells and test circuits shows very good agreement with SPICE BSIM4 transistor-level simulation both for nominal delay and for statistical Monte Carlo analyses.

A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs

Logic-level estimators of leakage currents, in nanoscale standard-cell-based designs, are relevant for the dramatic speed advantage with respect to analog SPICE-level simulation. We propose a novel logic-level leakage estimation model based on the characterization of voltages at the internal nodes of digital cells, in conjunction with the characterization of leakage currents in a single field-effect transistor (FET) device and with the input-dependent Kirchhoff current law expression of the total current in the cell topology. The voltage-based nature of the approach simplifies the inclusion of supply voltage variation/scaling impact, as well as of output voltage drop (loading effect), on leakage currents. The method has been implemented in hardware description language models of a complete cell library. Exhaustive tests report average accuracy below 1% error in 22-nm CMOS and 20-nm FinFET technologies, when compared with SPICE BSIM simulation results.

Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops

Abstract The assessment of noise margins and the related probability of failure in digital cells has growingly become essential, as nano-scale MOSFET and FinFET technologies are confronting reliability issues caused by aging mechanisms, such as NBTI and PBTI, and variability in process parameters. The effect of such phenomena on system level operation is particularly related to the Static Noise Margins (in idle and read mode) and the Write Noise Margins of memory elements. While Static Noise Margins have been studied in the past, in this work we calculated and compared the effect of process variations and NBTI/PBTI aging on the Write Noise Margins of various MOSFET- and FinFET-based flip-flop cells. The massive transistor-level Monte Carlo simulations produced both nominal (i.e. mean) values and associated standard deviations of the WNMs of the flip-flops. This allowed calculating the consequent write failure probability as a function of an input voltage shift, and assessing a comparison for robustness among different circuit topologies and technologies. Temperature and voltage dependence is also included in the analysis.

Novel approaches to quantify failure probability due to process variations in nano-scale CMOS logic

Estimating the failure probability of nano-scale generic logic cells is a key point for the evaluation of digital system reliability. Noise-induced input variations with process-induced threshold voltage variations affect the probability of correct operation of logic cells. This work quantitatively analyses the probability of invalid output of a cell by introducing novel analytical and semi-analytical approaches in comparison with SPICE Monte-Carlo verification approach.

Safe operation region characterization for quantifying the reliability of CMOS logic affected by process variations

Technology parameter variations combined with voltage noise can become a major cause of logic errors in digital circuits. This presentation brings in the idea of “safe operation region” to permit a robust analytical Monte Carlo evaluation of the reliability of logic circuits in a given technology, avoiding time-consuming SPICE-level or device-level Monte Carlo simulations. The application of the approach is demonstrated for the case of a 22 nm bulk CMOS process.

Using safe operation regions to assess the error probability of logic circuits due to process variations

Process variations in conjunction to voltage noise can be responsible of logic errors in digital circuits. The variations in process-induced parameters affect the probability of noise-induced faulty operation of digital logic cells. This work introduces the concept of “safe operation region” to allow an efficient Monte Carlo evaluation of the associated error probability, avoiding time-consuming circuit level or device level Monte Carlo simulations.

Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops

The estimation of dependable noise margins in digital cells is increasingly significant as nano-scale CMOS technology is facing true reliability issues. On one hand, a major concern comes from circuit aging mechanisms, such as NBTI, which degrade the reliability of circuit operation over time. On the other hand, variability in technology parameters results in affecting reliability. The impact of such phenomena is particularly related to the noise margins in the memory elements of a design, since a wrong stored logic value results in an upset of the system state. This work quantifies and compares the joint effect of process variations and of NBTI aging over the years on the real noise margins of several flip-flop cells. The huge amount of transistor level Monte Carlo simulations produced both nominal (i.e. average) values and associated standard deviations of the noise margins of the selected flip-flops. A possible concept of utilization of the acquired noise margin data is also reported.

Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores

FPGA-synthesizable soft-processor cores are commonly used in many digital system applications with low-medium production volume, to control heterogeneous dedicated computational units and I/O units. In such contexts, the inherently multi-tasking nature of the processor operation demands for a cost-effective and energy-efficient multi-threaded execution, either as multi-core architecture or multi-threaded single-core. This work presents an experimental exploration of microarchitecture design solutions for multi-threaded soft processor core implementations on FPGA. We report detailed quantitative results on resource utilization, performance and energy efficiency of the different solutions, varying the pipeline organizations, thread pool size, active thread count and voltage.

A general design methodology for synchronous early-completion-prediction adders in nano-CMOS DSP architectures

Synchronous early-completion-prediction adders (ECPAs) are used for high clock rate and high-precision DSP datapaths, as they allow a dominant amount of single-cycle operations even if the worst-case carry propagation delay is longer than the clock period. Previous works have also demonstrated ECPA advantages for average leakage reduction and NBTI effects reduction in nanoscale CMOS technologies. This paper illustrates a general systematic methodology to design ECPA units, targeting nanoscale CMOS technologies, which is not available in the current literature yet. The method is fully compatible with standard VLSI macrocell design tools and standard adder structures and includes automatic definition of critical test patterns for postlayout verification. A design example is included, reporting speed and power data superior to previous works.

Geometry Scaling Impact on Leakage Currents in FinFET Standard Cells Based on a Logic-Level Leakage Estimation Technique

Static power consumption is one of the most critical issues in CMOS digital circuits, and FinFET technology is being recognized as a valid solution for the problem. In this chapter, we utilize a logic-level leakage current estimation technique relying on an internal node voltage-based model. The model is implemented in the form of VHDL packages. By utilizing the capability of the model, the behavior of major leakage component has been analyzed separately for FinFET technology scaling over single- and multi-stage digital standard cells.