Francis Jutand

A single chip video rate 16×16 discrete cosine transform

The Discrete Cosine Transform [1] is a good but computation consuming first step of many image coding and compression algorithms for good quality, low rate transmissions. A low-cost implementation of a high-speed DCT operator would lower the price of CODEC and could open new fields of applications for DCT in real time image processing. This paper presents a one chip operator, achieving a full 16 × 16 DCT computation at video rate. Algorithmic, architectural and implementation choices combined with a careful optimization of the layout have made it possible to design a reasonnable size chip exhibiting such high performance.

VLSI Architecture for a one chip video median filter

Real-time image processing in an application environment needs a set of low-cost implementations of various algorithms. This paper presents a one chip VLSI median filter based on a systolic processor and working at video rate. It includes its own memory and can be used without any image memory for on-line processing. The architectural choices have made it possible to design a small size chip with a high performance level.

An optimized VLSI architecture for a multiformat discrete cosine transform

This communication presents an optimized architecture providing the computation power and the versatility that are required for the real-time processing of various blocks format (from 4*4 to 16*16) and for direct/inverse Discrete Cosine Transform. To achieve a realistic single chip implementation, different architectures have been compared. Circuits based on the most efficient architecture will be used for a real-time coder/decoder of color images.

VLSI architectures for dynamic time warping using systolic arrays

Dynamic Time Warping is implemented using an array of identical processing elements. Each processing element is designed to compute a local distance and update a global measure of dissimilarity. It is made up of 1900 transistors using a 2.5 micron NMOS technology. 25 processing elements and their local interconnections fit within 35mm2 of silicon that can be packaged in a standard 40 pin packaging. A single chip can handle 300 words in real time. An array of 22 chips will recognize within 200msec a syllable size pattern from a set of 6000. Various applications are taken up.