Nicolas Demassieux

VLSI Architecture for a one chip video median filter

Real-time image processing in an application environment needs a set of low-cost implementations of various algorithms. This paper presents a one chip VLSI median filter based on a systolic processor and working at video rate. It includes its own memory and can be used without any image memory for on-line processing. The architectural choices have made it possible to design a small size chip with a high performance level.

High speed low power architecture for memory management in a Viterbi decoder

The management of the surviving-path memory in the Viterbi algorithm is generally performed by Trace-Back or Exchange Register. It has been shown that combining these two techniques leads to efficient realisation. In the present work, formal expressions of computational power, memory and latency are presented for several classes of algorithms. For v=4, L=64 Viterbi decoder, this formalism helps to find two algorithms that respectively reduce by a factor of 4 and 7 respectively, the computational power compared to a direct Exchange Register. Implementation results-place&route netlist generated through VHDL synthesis-and theoretical results are in concordance.

Optimal VLSI architecture for distributed arithmetic-based algorithms

Digital signal processing algorithms often use inner product as basic computation. In this paper we propose a new design methodology for synthesizing an optimal VLSI architecture implementing a real-time Distributed Arithmetic-based inner product. Our design methodology considers the design space as bidimensional one. In the first dimension we consider all possible input data parallelisations: from bit-serial to bit-parallel. In the second dimension we consider all possible lookup-table partitioning. Using a new ROM generic model, expressions are developed for area and maximum input data bandwidth, which allows to have an explicit formulation of the area-bandwidth tradeoff. Finally, for a given set of application constraints (inner product size and data bandwidth), we exhibit the optimal architectural parameters that provide the smallest chip area.<<ETX>>

VLSI architectures for dynamic time warping using systolic arrays

Dynamic Time Warping is implemented using an array of identical processing elements. Each processing element is designed to compute a local distance and update a global measure of dissimilarity. It is made up of 1900 transistors using a 2.5 micron NMOS technology. 25 processing elements and their local interconnections fit within 35mm2 of silicon that can be packaged in a standard 40 pin packaging. A single chip can handle 300 words in real time. An array of 22 chips will recognize within 200msec a syllable size pattern from a set of 6000. Various applications are taken up.

A generalized precompiling scheme for surviving path memory management in Viterbi decoders

The management of the surviving path memory in Viterbis algorithm is generally performed by trace-back or exchange-register. A generalized method using precompiled trace-backs is presented. Resolution by a graphical method is proposed. Three examples are solved.<<ETX>>

Optimization of real-time VLSI architectures for distributed arithmetic-based algorithms: application to HDTV filters

In order to implement the distributed arithmetic-based inner product, we propose two different architectures: ROM-based architecture and hardwired architecture. To define the optimal VLSI architecture, we consider all possible input data parallelisations: from bit-serial to bit-parallel. Then, for each parallelisation, we consider all possible partitions of the lookup-table. For both ROM-based and hardwired architectures, expressions are developed for area and speed, which allow us to have an explicit formulation of the area-speed tradeoff. Then, for given application constraints (inner product size and input data bandwidth), we exhibit the optimal architectural parameters that provide the smallest chip area. Finally, we show that, at any given application constraints, the hardwired architecture provides a smaller area than the ROM-based architecture.<<ETX>>

Real-time architecture for large displacements estimation

In this paper, we present a new motion estimation architecture for large displacements estimation. An efficient differential block recursive algorithm is used to orient searching for a match and save computation power. Multiresolution and multiprediction approaches accelerate the algorithm convergence. Data multiplexing and pipeline allow real-time processing for standard video frequencies such as CCIR 601.

Memory-I/O tradeoff and VLSI implementation of lapped transforms for image processing

The authors describe a new system architecture for real-time two-dimensional image block processing by separable lapped transforms (LTs). The main advantage of this image block 2-D LT is the reduction of the transposition memory size and its on-chip integration. The tradeoff between input/output (I/O) throughput and on-chip memory size is discussed. The design of the transposition memory and its VLSI complexity performacne in terms of areas and speed are presented.<<ETX>>

Décodage de Constellations Optimisées Pour le Canal de Rayleigh

It has recently been shown that a new class of d-dimensional non-QAM constellations matched for the Rayleigh fading channel (π-constellations), allows a d-order diversity without addition of redundancy [6–8]. Combined with traditional coding techniques, π-constellations are very efficient. However, the decoding algorithm of these constellations is far more complicated than that for qam-constellations. A sub-optimal algorithm for the decoding of π-constellations is proposed in this work. An example of application for 4 bit/Hz.s spectral efficiency with a 4-D π-constellations is given and the VLSI architecture of the decoder is described. The implementation, in a 0.8 μm standard cell technology, can be achieved with a 72 K gate circuit, with a binary rate of 32 Mbit/s and, from simulation, a binary error rate of 10- 3 for a snr of 14 dB.RésuméIl a été récemment montré que l’utilisation de constellations à d dimensions spécialisées pour le canal de Rayleigh permettait d’obtenir une diversité d’ordre d sans aucun codage (constellation π) [6–8]. Cependant, le décodage de ces constellations est très complexe et rend problématique leur utilisation dans des applications haut débit. Un algorithme de décodage sous-optimal permettant de décoder les constellations π en temps réel est présenté. Un exemple d’application d’efficacité spectrale 4 bit/Hz.s est décrit jusqu à la réalisation vlsi. Le nombre total déportes du décodeur associé est de 72 000 portes (technologie 0.8 μn en cellule standard), le débit binaire de 32 Mbit/s. Les simulations montrent que le taux d’erreurs binaires pour un rapport signal à bruit de 14 dB est de 10-3.Il a ete recemment montre que l’utilisation de constellations a d dimensions specialisees pour le canal de Rayleigh permettait d’obtenir une diversite d’ordre d sans aucun codage (constellation π) [6–8]. Cependant, le decodage de ces constellations est tres complexe et rend problematique leur utilisation dans des applications haut debit. Un algorithme de decodage sous-optimal permettant de decoder les constellations π en temps reel est presente. Un exemple d’application d’efficacite spectrale 4 bit/Hz.s est decrit jusqu a la realisation vlsi. Le nombre total deportes du decodeur associe est de 72 000 portes (technologie 0.8 μn en cellule standard), le debit binaire de 32 Mbit/s. Les simulations montrent que le taux d’erreurs binaires pour un rapport signal a bruit de 14 dB est de 10-3.

A real-time discrete cosine transform chip

One of the main problems in telecommunications is the optimization of spectrum use for broadcasting and the optimization of channel bandwidth for point-topoint transmission. Given the wide bandwidth of video signals, until recently image transmission was limited to the broadcasting of television signals or to expensive videoconferencing applications. Similarly, the storage of moving images was costly or of average or poor quality. Image-compression techniques, although feasible in theory, were hard to implement in practice and costly, given existing technology. During the last few years, the hope of using digital images for both transmission and storage stimulated considerable progress in compression algorithms. Today, at the start of the 199Os, we are seeing an explosion in applications, including the coding of still images for transmission over integrated services digital networks (ISDNs), the transmission of moving images of lesser quality for picture phones, and storage on compact discs of still and moving images (compact disc ROM and interactive compact discs). Simultaneously, we are seeing a new convergence of telecommunications and computers. After compression, still and moving images have a bit rate comparable to that of sound and computer data, meaning they can be handled by computer hardware and software. As a result, subscriber terminals, television sets, videocassette recorders, camcorders, and microcomputers will make greater use of the entry, transmission, compression, and processing of still and moving images. Introduction in the medium term of highdefinition television (HDTV) and picture-phone service will broaden the use of image compression in professional and consumer products. Lastly, the technology, particularly in microelectronics, has advanced even further. Application-spe-