Franck Foussadier

3D Mask modeling with Oblique incidence and Mask Corner rounding effects for the 32nm node

The perpetual shrinking in critical dimensions in semiconductor devices is driving the need for increased resolution in optical lithography. Increasing NA to gain resolution also increases Optical Proximity Correction (OPC) model complexity. Some optical effects which have been completely neglected in OPC modeling become important. Over the past few years, off-axis illumination has been widely used to improve the imaging process. OPC models which utilize such illumination still use the thin film mask approximation (Kirchhoff approach), during optical model generation, which utilizes a normal incidence. However, simulating a three dimensional mask near-field using an off-axis illumination requires OPC models to introduce oblique incidence. In addition, the use of higher NA systems introduces high obliquity field components that can no longer be assimilated as normal incident waves. The introduction of oblique incidence requires other effects, such as corner rounding of mask features, to be considered, that are seldom taken into account in OPC modeling. In this paper, the effects of oblique incidence and corner rounding of mask features on resist contours of 2D structures (i.e. line-ends and corners) are studied. Rigorous electromagnetic simulations are performed to investigate the scattering properties of various lithographic 32nm node mask structures. Simulations are conducted using a three dimensional phase shift mask topology and an off-axis illumination at high NA. Aerial images are calculated and compared with those obtained from a classical normal incidence illumination. The benefits of using an oblique incidence to improve hot-spot prediction will be discussed.

Correction of long-range effects applied to the 65-nm node

Specifications for CD control on current technology nodes have become very tight, especially for the gate level. Therefore all systematic errors during the patterning process should be corrected. For a long time, CD variations induced by any change in the local periodicity have been successfully addressed through model or/and rule based corrections. However, if long-range effects (stray light, etch, and mask writing process...) are often monitored, they are seldom taken into account in OPC flows. For the purpose of our study, a test mask has been designed to measure these latter effects separating the contributions of three different process steps (mask writing, exposure and etch). The resulting induced CD errors for several patterns are compared to the allowed error budget. Then, a methodology, usable in standard OPC flows, is proposed to calculate the required correction for any feature in any layout. The accuracy of the method will be demonstrated through experimental results.

65nm OPC and design optimization by using simple electrical transistor simulation

In the context of 65nm logic technology where gate CD control budget requirements are below 5nm, it is mandatory to properly quantify the impact of the 2D effects on the electrical behavior of the transistor [1,2]. This study uses the following sequence to estimate the impact on transistor performance: 1) A lithographic simulation is performed after OPC (Optical Proximity Correction) of active and poly using a calibrated model at best conditions. Some extrapolation of this model can also be used to assess marginalities due to process window (focus, dose, mask errors, and overlay). In our case study, we mainly checked the poly to active misalignment effects. 2) Electrical behavior of the transistor (Ion, Ioff, Vt) is calculated based on a derivative spice model using the simulated image of the gate as an input. In most of the cases Ion analysis, rather than Vt or leakage, gives sufficient information for patterning optimization. We have demonstrated the benefit of this approach with two different examples: -design rule trade-off : we estimated the impact with and without misalignment of critical rules like poly corner to active distance, active corner to poly distance or minimum space between small transistor and big transistor. -Library standard cell debugging: we applied this methodology to the most critical one hundred transistors of our standard cell libraries and calculate Ion behavior with and without misalignment between active and poly. We compared two scanner illumination modes and two OPC versions based on the behavior of the one hundred transistors. We were able to see the benefits of one illumination, and also the improvement in the OPC maturity.

Process Control for 45 nm CMOS logic gate patterning

This paper present an evaluation of our CMOS 45nm gate patterning process performance based on immersion lithography in a production environment. A CD budget breakdown is shown detailing lot to lot, wafer to wafer, intrawafer, intrafield and proximity CD uniformity characterization. Emphasis is given on scatterometry library development and deployment. We also look more into detail to focus effect on CD control. Finally status of overlay performance with immersion lithography is also presented.

Demonstration of an effective flexible mask optimization (FMO) flow

The 2x nm generation of advanced designs presents a major lithography challenge to achieve adequate correction due to the very low k1 values. The burden thus falls on resolution enhancement techniques (RET) in order to be able to achieve enough image contrast, with much of this falling to computational lithography. Advanced mask correction techniques can be computationally expensive. This paper presents a methodology that enables advanced mask quality with the cost of much simpler methods. Brion Technologies has developed a product called Flexible Mask Optimization (FMO) which identifies hotspots, applies an advanced technique to improve them, performs model based boundary healing to reinsert the repaired hotspot cleanly (without introducing new hotspots), and then performs a final verification. STMicroelectronics has partnered with Brion to evaluate and prove out the capability and performance of this approach. The results shown demonstrate improved performance on 2x nm node complex 2D hole layers using a hybrid approach of rule based sub resolution assist features (RB-SRAF) and model based SRAF (MB-SRAF). The effective outcome is to achieve MB-SRAF levels of quality but at only a slightly higher computational cost than a quick, cheap rule based approach.

Sensitivity of a variable threshold model toward process and modeling parameters

The quality of model-based OPC correction depends strongly on how the model is calibrated in order to generate a resist image as close to the desired shapes as possible. As the k1 process factor decreases and design complexity increases, the correction accuracy and the model stability become more important. It is also assumed that the stability of one model can be tested when its response to a small variation in one or several parameters is small. In order to quantify this, the small-variation method has been tested on a variable threshold based model initially optimized for the 65nm node using measurements done with a test pattern mask. This method consists of introducing small variations to one input model parameter and analyzing the induced effects on the simulated edge placement error (EPE). In this paper, we study the impact of small changes in the optical and resist parameters (focus settings, inner and outer partial coherent factors, NA, resist thickness) on the model stability. And then, we quantify the sensitivity of the model towards each parameter shift. We also study the effects of modeling parameters (kernel count, model fitness, optical diameter) on the resulting simulated EPE. This kind of study allows us to detect coverage or process window problems. The process and modeling parameters have been modified one by one. The ranges of variations correspond to those observed during a typical experiment. Then the difference in simulated EPE between the reference model and the modified one has been calculated. Simulations show that the loss in model accuracy is essentially caused by changes in focus, outer sigma and NA and lower values of optical diameter and kernel count. Model results agree well with a production layout.

Through-process window resist modelling strategies for the 65 nm node

Ensuring robust patterning after OPC is becoming more and more difficult due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. As a result, post-OPC verification methods have become indispensable tools for avoiding pattern printing issues. The majority of these methods are primarily based on lithographic simulations of pattern printing behaviour across dose and focus variations. The models used for these simulations are compact optical models combined with one single resist model. Even if very predictive resist models exist, they have often a large number of parameters to fit and suffer from long computing times to execute the simulations. Simplified resist models are thus needed to enhance run-time computing during simulation. The objective of this study is to test the predictability of such resist models across the process window. Two different resist models will be considered in this study. The first resist model is a pure variable threshold resist model. The second resist modelling approach is a simplified physical model which uses Gaussian convolutions and a constant threshold to model resist printing behaviour. The study concentrates on poly layer patterning for the 65 nm node. Examples of specific simulations obtained with the two different techniques are compared against experimental results.

Characterization of inverse SRAF for active layer trenches on 45-nm node

Patterning isolated trenches for bright field layers such as the active layer has always been difficult for lithographers. This patterning is even more challenging for advanced technologies such as the 45-nm node where most of the process optimization is done for minimum pitch dense lines. Similar to the use of scattering-bars to assist isolated lines structures, we can use inverse Sub Resolution Assist Features (SRAF) to assist the patterning of isolated trenches structures. Full characterization studies on the C45 Active layer demonstrate the benefits and potential issues of this technique: Screen Inverse SRAF parameters (size, distance to main feature) utilizing optical simulation; Verify simulation predictions and ensure sufficient improvement in Depth of Focus and Exposure latitude with silicon process window analysis; Define Inverse SRAF OPC generation script parameters and validate, with accurate on silicon, measurement characterization of specific test patterns; Maskshop manufacturability through CD measurements and inspection capability. Finally, initial silicon results from a 45nm mask are given with suggestions for additional optimization of inverse SRAF for trenches.

Outliers detection by fuzzy classification method for model building

Optical Proximity Correction (OPC) is used in lithography to increase the achievable resolution and pattern transfer fidelity for IC manufacturing. Nowadays, immersion lithography scanners are reaching the limits of optical resolution leading to more and more constraints on OPC models in terms of simulation reliability. The detection of outliers coming from SEM measurements is key in OPC [1]. Indeed, the model reliability is based in a large part on those measurements accuracy and reliability as they belong to the set of data used to calibrate the model. Many approaches were developed for outlier detection by studying the data and their residual errors, using linear or nonlinear regression and standard deviation as a metric [8]. In this paper, we will present a statistical approach for detection of outlier measurements. This approach consists of scanning Critical Dimension (CD) measurements by process conditions using a statistical method based on fuzzy CMean clustering and the used of a covariant distance for checking aberrant values cluster by cluster. We propose to use the Mahalanobis distance [2] in order to improve the discrimination of the outliers when quantifying the similarity within each cluster of the data set. This fuzzy classification method was applied on the SEM CD data collected for the Active layer of a 65 nm half pitch technology. The measurements were acquired through a process window of 25 (dose, defocus) conditions. We were able to detect automatically 15 potential outliers in a data distribution as large as 1500 different CD measurement. We will discuss about these results as well as the advantages and drawbacks of this technique as automatic outliers detection for large data distribution cleaning.

Impact of modelisation pixel size on OPC consistency

In advanced technology nodes, due to accuracy and computing time constraint, OPC has shifted from discrete simulation to pixel based simulation. The simulation is grid based and then interpolation occurs between grid points. Even if the sampling is done below Nyquist rate, interpolation can cause some variations for same polygon placed at different location in the layout. Any variation is rounded during OPC treatment, because of discrete numbers used in OPC output file. The end result is inconsistency in post-OPC layout, where the same input polygon will give different outputs, depending on its position and orientation relative to the grid. This can have a major impact in CD control, in structures like SRAM for example, where mismatching between gates can cause major issue. There are some workarounds to minimize this effect, but most of them are post-treatment fix. In this paper, we will try to identify and solve the root cause of the problem. We will study the relationship between the pixel size and the consistency of post OPC results. The pixel size is often set based on optical parameters, but it might be possible to optimize it around this value to avoid inconsistency. One can say that the optimization will highly depend on design and not be possible for a real layout. As the range of pitch used in a design tends to decrease, thanks to fix pitch layouts, we may optimize pixel size for a full layout.