François Pêcheux

An OFDMA based RF interconnect for massive multi-core processors

A paradigm shift is apparent in Chip Multiprocessor (CMP) design, as the new performance bottleneck is becoming communication rather than computation. It is widely provisioned that number of cores on a single chip will reach thousands in a decade. Thus, new high rate interconnects such as optical or RF have been proposed by various researchers. However, these interconnect structures fail to provide essential requirements of heterogeneous on-chip traffic; bandwidth reconfigurability and broadcast support with a low complex design. In this paper we investigate the feasibility of a new Orthogonal Frequency Division Multiple Access (OFDMA) RF interconnect for the first time to the best of our knowledge. In addition we provide a novel dynamic bandwidth arbitration and modulation order selection policy, that is designed regarding the bimodal on-chip packets. The proposed approach decreases the average latency up to 3.5 times compared to conventional static approach.

UVM-SystemC-AMS based framework for the correct by construction design of MEMS in their real heterogeneous application context

Each new embedded system tends to integrate more sensors with tight software-driven control, digitally assisted analog circuits, and heterogeneous structure. A more responsive simulation environment is needed to support the co-design and verification of such complex architectures including all its digital hardware/software and analog/multi-physical aspects using Multi-Disciplinary Virtual Prototyping (MDVP). Taking a Micro-Electro-Mechanical System (MEMS) vibration sensor as an example, we introduce a reusable framework based on the state-of-the-art technologies SystemC AMS, Finite Elements/Reduced-Order modeling, and UVM to design, simulate, and verify such systems in their real application context.

SystemC-AMS simulation of a biaxial accelerometer based on MEMS model order reduction

This paper proposes a framework for system-level modeling and simulation of a Micro Electro-Mechanical System (MEMS). We show how a reduced-order model of MEMS can be integrated into SystemC-AMS. We propose the use of an external linear algebra library and alternative time integration method. Both are used to customize a Timed Data Flow (TDF) module to address MEMS modeling. Experiments are conducted on a biaxial accelerometer to verify its response to a ramp impulse. Our implementation runs about twice as fast as the state space resolution currently implemented in SystemC-AMS 2.0. Results highlight potential improvements of SystemC-AMS standard to correctly simulate the analog behavior of MEMS devices.

Pre-simulation elaboration of heterogeneous systems: The SystemC multi-disciplinary virtual prototyping approach

Designers of the upcoming digital-centric More-than-Moore systems are lacking a common design and simulation environment able to efficiently manage all the multi-disciplinary aspects of its components of various nature that closely interact with each other. A key to successful design and verification lies in a SystemC-based virtual prototyping environment that is able to simulate a complex heterogeneous system as a whole, for which each component is described and solved using the most appropriate Model of Computation (MoC). In this paper, we present a new generic MoC-independent elaboration scheme that aims at preparing a Virtual Prototype (VP) for simulation. It requires to check the correct composition of the system model through dimensional analysis, to explore the model structure to identify involved MoC and interfaces between MoCs, and to detect the underlying dependencies. Eventually, information extracted from the exploration allow the instantiation of MoC-specific solvers. To soundly handle the global model execution with a Discrete Event (DE) kernel as the main solver, synchronization mechanisms with master-slave semantics within the model structure are implicitly deduced.

A Dynamically Reconfigurable RF NoC for Many-Core

With the growing number of cores on chips, conventional electrical interconnects reach scalability limits, leading the way for alternatives like Radio Frequency (RF), optical and 3D. Due to the variability of applications, communication needs change over time and across regions of the chip. To address these issues, a dynamically reconfigurable Network on Chip (NoC) is proposed. It uses RF and Orthogonal Frequency Division Multiple Access (OFDMA) to create communication channels whose allocation allows dynamic reconfiguration. We describe the NoC architecture and the distributed mechanism of dynamic allocation. We study the feasibility of the NoC based on state of the art components and analyze its performances. Static analysis shows that, for point to point communications, its latency is comparable with a 256-node electrical mesh and becomes lower for wider networks. A major feature of this architecture is its broadcast capacity. The RF~NoC becomes faster with 32 nodes, achieving a x3 speedup with 1024. Under realistic traffic models, its dynamic reconfigurability provides up to x6 lower latency while ensuring fairness.

SystemC-MDVP modelling of pressure driven microfluidic systems

Systems composed by multiple physical domains (i.e. mechanical, biological, optical, fluidic, etc.) and usually controlled by an embedded HW/SW circuit cannot, up to date, be jointly simulated in order to correctly specify, dimension and verify these multi-domain microelectronics assisted systems at an early system level stage. This paper describes part of the work that it is being carrying out (under the CATRENE CA701 project) in order to define an open framework, based on SystemC-AMS, with the aim to extend this language to support multiple physical domains. The proposed extensions for being able to model a micro-fluidic system are going to be exposed. Two approaches have been selected: to model the fluid analytically based on the Poiseuille flow theory and to model the fluid numerically following the SPH (Smoothed Particle Hydrodynamics) approach. Both modeling techniques are, by now, encapsulated under the TDF (Timed Data Flow) MoC (Model of Computation) of SystemC-AMS.

Flexible Radio Interface for NoC RF-Interconnect

This paper introduces flexible radio techniques inside integrated circuits in order to tackle the interconnect issue for many-core chips. We propose to take benefits from OFDMA for a RF-interconnect associated to a carrier allocation policy and adaptive modulation. A 20 GHz bandwidth is shared between 32 tile sets made of 32 tiles of 4 cores each, for a 4096 cores chip. We adopt a cognitive radio approach in order to dynamically share 1024 carriers, which avoids inter-cluster communication contention and decreases latency compared to conventional static approaches.

Towards the simulatable specification of a highly customisable SystemC AMS alternator model in its multi-domain environment

This paper presents a refinable and customisable alternator model with its heterogeneous environment, all implemented in SystemC and SystemC-AMS. The virtual prototype can be configured easily, and the embedded software can be changed at any time. Experience has shown that the overall development time can be reduced. Indeed, with a high-level configurable description of the environment and a refinable synchronous machine system model, electronic designers can easily evaluate performances according to architecture exploration.

Pre-simulation symbolic analysis of synchronization issues between discrete event and timed data flow models of computation

The SystemC AMS extensions support heterogeneous modeling and make use of several Models of Computation (MoCs) that operate on different time scales in the Discrete Event (DE), Discrete Time (DT), and Continuous Time (CT) domains. The simulation of such heterogeneous models may raise synchronization problems that are hard to diagnose and to fix, especially when considering multi-rate data flow parts. In this paper, we show how to formally analyze the execution of Timed Data Flow (TDF) models including their interaction with the DE domain by converting the synchronization mechanics into a Coloured Petri Net (CPN) equivalent. The developed symbolic execution algorithm for the CPN allows to detect all DE-TDF synchronization issues before simulation and to propose appropriate sample delay settings for the TDF converter ports to make the system schedulable. The presented technique is validated with a case study including a vibration sensor model and its digital front end.

Un réseau sur puce RF reconfigurable dynamiquement pour les many-cœurs

La multiplication du nombre de cœurs de calcul presents sur une meme puce va de pair avec une augmentation des besoins en communication. De plus, la variete des applications s’executant sur la puce provoque une heterogeneite spatiale et temporelle des communications. C’est pour repondre a ces problematiques que nous presentons dans cet article un reseau d’interconnexion sur puce dynamiquement reconfigurable utilisant la Radio Frequence (RF). L’utilisation de la RF permet d’avoir plus de bande passante en minimisant la latence. La possibilite de reconfigurer dynamiquement le reseau permet de s’adapter a la variabilite des communications. Nous presentons les raisons du choix de la RF par rapport aux autres nouvelles technologies du domaine que sont l’optique et la 3D, l’architecture detaillee de ce reseau et d’une puce le mettant en œuvre ainsi que l’evaluation de sa faisabilite et de ses performances. Un des avantages de ce reseau d’interconnexion RF est la possibilite de faire du broadcast sans surcout par rapport aux communications point-a-point, ouvrant ainsi de nouvelles perspectives en termes de gestion de la coherence memoire notamment.