Marie-Minerve Louërat

Simulation-based hierarchical sizing and biasing of analog firm IPs

This paper presents a simulation-based hierarchical sizing and biasing tool for analog integrated circuits design. The tool allows the designer to express the sizing procedure in terms of sizing and biasing operators. These operators are technology independent, hence the documented procedure can be easily ran over different technologies. A procedure has been proposed for a single-ended two-stage operational amplifier and evaluated over 130nm, 65nm and 45nm technologies. The results prove the efficiency of the proposed tool.

A novel CAD framework for substrate modeling

This paper presents a novel Computer-Aided-Design (CAD) framework for 3D extraction of the substrate electrical network. The proposed CAD tool (framework) models efficiently the minority carrier propagation inside substrate network especially for smart power ICs. Today, the minority carrier propagation into the substrate is ignored in existing SPICE simulators. It can be simulated using finite element methods in TCAD. Generally, TCAD simulations are accurates but take long time. Thus, they become of limited help for large scale ICs involving hundreds of transistors. In the context of the FP7 AUTOMICS project, the extraction tool will take into consideration the minority carriers effects. It will allow the designer to predict the minority carrier propagation through the substrate. This can be useful in evaluation the efficiency of ESD protection and latchup faults due to this leackage current in the substrate specially in HV/HT applications. With the proposed substrate network, the three-dimensional layout parasitics are constructed and substrate noise is simulated before first silicon fabrication. A simple diode example is illustrated to demonstrate the principal idea of the extraction tool.

Hierarchical Graph-Based Sizing for Analog Cells Through Reference Transistors

In this paper, an algorithm for automatic sizing and operating point computation of hierarchical knowledge-based analog cells is presented. The algorithm assumes that an analog cell is described as a hierarchy of devices and modules inside our dedicated framework CAIRO+. Within devices, the concept of the reference transistor is elaborated. The latter is used to construct device dependency graphs for each device. Module dependency graphs are constructed by merging graphs of all children modules and devices. Inside each device, the reference transistor controls the sizing and biasing of the whole device. It propagates electrical parameters to secondary transistors. The used propagation technique ensures that all the device constraints are satisfied by construction. The algorithm was used to size and bias a two-stage single-ended OTA amplifier. It proved to be successful in DC operating point calculation in the context of hierarchical knowledge-based framework

Background time skew calibration for time-interleaved ADC using phase detection method

This paper presents a background time skew calibration technique for time-interleaved analog-to-digital converter (TIADC). It depends on the phase detection between a digitally generated calibration signal and the output of each ADC in the system that suffers from time skew mismatch. Digitally controlled delay lines (DCDL) are used to minimize the time skew mismatches among the clock routes. The calibration technique behaviors are theoretically analysed and verified by simulations. A 12-bit 4-channel, 800 MS/s TIADC is used as an example.

Automatic model refinement of GmC integrators for high-level simulation of continuous-time Sigma-Delta modulators

A ΣΔ GmC integrator refinement flow is presented. The classically simplified GmC integrator small-signal model was upgraded to be extremely accurate by considering the complete transistor small-signal model. A circuit-level knowledge-based tool was used to execute the designer defined sizing procedure and to extract small signal parameters. By associating the symbolic transfer function to small-signal parameters, the flow, entirely implemented with C++, is able to compute poles and zeros to permit precise behavioral simulations. A 2nd order ΣΔ modulator was chosen to visualize performance degradations while the specifications were not achievable.

Fast multidimensional optimization of analog circuits initiated by monodimensional global Peano explorations

A fast design space exploration of analog firm intellectual properties (IP) based on Peano-like paths (piecewise linear and monodimensional) is presented. First, the n-dimensional design space is globally explored following those Peano curves, which are obtained by varying only 1 design variable at a time using a fixed step size. Each variable is taken within a given range. During exploration, the best x-percentile points are retained. After varying globally the n variables, a Nelder-Mead simplex optimization is performed using each of the best points as an initial point. Successive p-variable partitioning of the n-dimensional design space (with p ?? n ) are applied to adapt the simplex optimization to large dimensions. The proposed exploration technique is combined with a simulation-based hierarchical sizing and biasing methodology to size and bias analog firm IPs. This combined approach has been successfully applied to size and bias a Constant Voltage Reference (CVR) in a 5V SOI 1 µ m technology. The results illustrate the effectiveness and accuracy of the proposed approach. HighlightsWe develop a novel global optimization engine based on Peano curves.Adding a hierarchical sizing renders the optimization interactive.We apply the proposed approach on a CVR circuit 1 µ m XFAB SOI technology.

Split ADC digital background calibration for high speed SHA-less pipeline ADCs

A bottom plate sampling switch sharing technique is proposed to enable split ADC calibration with high frequency inputs for Sample and Hold Amplifier-less (SHA-less) pipeline ADCs. The shared bottom plate switch ensures that both halves of the ADC sample the input at the same time, which restores the calibration accuracy for fast varying inputs without the presence of a front-end SHA, thereby significantly reducing area and power consumption. For further power reduction, a feedforward two stage amplifier has been used to push the speed of the amplifier at lower current consumption and low supply voltage. A 12-bit 200 MS/s pipeline ADC has been designed in 40 nm CMOS technology, and the transistor level simulations of the ADC prove the efficiency of the proposed technique to restore the split ADC calibration accuracy in SHA-less pipeline ADCs.

Design considerations for low gain amplifier in the MDAC of digitally calibrated pipelined ADCs

The goal of this paper is to provide design considerations for the use of low gain amplifier presents in the Multiplying Analog-to-Digital Converter (MDAC) of pipelined ADCs with gain error correction in the digital domain. Using low gain amplifier in the MDAC makes the pipelined ADC more susceptible to gain variation and harmonic distortion, impacting the ADC performance. Theory and simulations are presented to provide design insight into the trade-off between minimum gain and its variations to preserve the calibrated ADC performance. These considerations are demonstrated on the MDAC of a 12 bit digitally calibrated pipelined ADC designed in 40nm CMOS technology.

Automatic stress effects computation based on a layout generation tool for analog IC

This paper studies the matching and the stress effect problems that appear in deep submicron CMOS technologies. These effects significantly affect the electrical behavior of CMOS transistors. We propose a method to compute stress effect parameters resulting from different layout styles such as interdigitated and symmetrical styles. We apply this method to a transistor device and a differential pair device. We also quantify the errors due to transistor folding and stress effects in 65nm CMOS technology for different device layouts. The results show the effectiveness of the proposed method.

An adaptive mesh refinement strategy of substrate modeling for smart power ICs

Substrate noise coupling due to minority carriers propagation in smart power integrated circuit becomes a critical issue specially for high voltage applications. Computer-Aided-Design modeling methodology for substrate parasitic-immune design was introduced. It is based on constructing a 3D substrate equivalent network. The substrate equivalent network consists of models of diodes and resistors that are capable of preserving the continuity of minority carriers. In this paper, an optimized meshing topology for substrate modeling is introduced. This meshing topology contributes significantly in the extracted component reduction and hence speeds up the simulation while improving the convergence of the simulator. A typical NPN bipolar transistor is used as case study. Comparing the proposed meshing topology to the basic meshing topology, the number of extracted components is reduced by 78% and the simulation time is lowered by 88%. SPICE-like analysis results confirm the accuracy of modeling approach with an acceptable relevant error (<;10%) compared to standard model. With the proposed meshing topology, it is feasible to model the substrate parasitic of more complex smart power integrated circuit.