François-Raymond Boyer

Space: a hardware/software systemC modeling platform including an RTOS

This work attempts to enhance the support of embedded software modeling with SystemC 2.0. We propose a top-down approach that first. lets designers specify their application in SystemC at a high abstraction level through a set of connected modules, and simulate the whole system. Then, the application is partitioned in two parts: software and hardware modules. Each partition can be connected to our platform that includes a commercial RTOS executed by an ARM ISS scheduled by the SystemC simulator. One of our major contributions is that we can easily move a module from hardware to software (and vice versa) to allow architectural exploration.

Performance improvement of configurable processor architectures using a variable clock period

Programmable and configurable processors are becoming increasingly popular for embedded wearable devices. In configurable processors technology it is a common practice to define specialized instructions in order to boost the performance of the device. These instructions may not fit in a single clock period and therefore, may require two clock periods for completion of a given task. In the past, we have proposed a method to generate a clock where each cycle can have a different length, and in this paper we investigate the performance gain it can give compared to standard clocking. Using our variable fractional clock period method, a gain of more than 10% in performance is easily obtained, with a maximum of 21%, compared to current best clocking techniques used in extensible configurable processors. We also show that the overall speedup of our method follows the well known Amdahls law, but without quantization of the acceleration factor.

A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs

In this paper, the authors propose two high-speed variable rate clock generator circuits that can synthesize frequencies which are fractional multiples of an input clock. The designs can switch between frequencies in a glitch-free manner, within a single clock cycle. In response to an N-phase reference clock, the first circuit can generate a clock of up to N times the reference frequency, whereas the second solution can generate up to N/2 times that frequency. The available synthesized frequencies are given by frefmiddotN/M , where M can be any integer greater than or equal to 1, depending on the circuit. The solutions were coded in VHDL, synthesized, placed and routed in TSMCs 180nm CMOS technology. Simulations using the extracted layout show that the proposed designs can operate with a reference frequency of up to 400MHz, yielding a maximum output clock of 4times the reference, or 1.6GHz. The designs were also validated with an implementation on Xilinxs Spartan 3 FPGA device.

Iterative Noise-Compensated Method to Improve LPC Based Speech Analysis

It is well known that linear predictive coding (LPC) performs well when the prediction coefficients are estimated from noise-free speech, and the system tends to degrade and perform poorly on noisy speech. This paper describes a method to minimize the degradation on the prediction coefficients in the presence of noise when an LPC analysis is used. In this method, a more accurate estimation of noise power is computed by using a simplified noise power spectral density (PSD) estimator. After an inverse discrete Fourier transform (DFT), the extracted noise autocorrelation coefficients are gradually subtracted from the coefficients derived from noisy speech according to an iterative processing scheme. The proposed processing scheme takes the absolute value of the estimated reflection coefficients as the decision criterion. It is shown that performing this iterative procedure on every autocorrelation lag ensures a substantial decrease in the degrading effects of noise, while the estimated autocorrelation matrix is guaranteed to be positive-definite. Experimental results indicate that the variance of the estimated prediction coefficients can be decreased significantly using the proposed method.

Design and optimization of a low complexity all-digital digital-to-analog converter

This paper presents a novel all-digital circuit topology for a digital-to-analog converter (DAC). It consists of series of inverters whose outputs are connected together. Depending on the thermometer code input, some inverters will have conducting PMOS whereas others will have conducting NMOS, thus providing an analog output. Even though the system is inherently non-linear, mathematical optimization has been done in order to improve its linearity. Due to process and temperature variations, the proposed DAC has a resolution that is limited to 3 bits in a 0.18μm CMOS technology. Transistor-level simulations using Cadences Spectre simulator have also been done to validate the theoretical results.

Direct digital synthesis-based all-digital phase-locked loop

In this paper, we present an architecture for a PLL that is based on DDS and that can be implemented using all-digital components. The local oscillator is based on a DDS that is clocked by a local oscillator and that is synchronized to a crystal reference using a negative feedback which is similar to a PLL. Even though the DDS uses a ring oscillator, the proposed design can provide a precise output clock in presence of process and temperature variations. The resulting system has deterministic jitter that is equal to 1 period of the ring oscillator. The system was validated using MATLAB/Simulink and was implemented on a Cyclone II FPGA. Measured experimental results confirm that the system works as expected.

A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs

In this paper, we propose a novel architecture of a hybrid phase-locked loop (PLL) that does not require conventional analog filters. The architecture replaces the loop filter by an Incrementer/Decrementer (INC/DEC), a digital-to-analog converter (DAC) and a charge pump. The proposed solution helps alleviate many of the problems encountered with analog loop filters, which become more prominent as technology scales down. In order to prove the validity of the architecture, the design was implemented at the schematic level in 180 nm TSMC CMOS technology. The design was simulated using SPECTRE in the Cadencepsilas Virtuoso analog environment, and results show that the proposed architecture performs as expected. When compared to an analog PLL with similar settling time, the proposed 180 nm design even provides 1.8 X better deterministic jitter.

A fast systolic priority queue architecture for a flow-based Traffic Manager

This paper presents a fast systolic priority queue architecture usable in a traffic manager. The purpose of the traffic manager is to schedule the departure of packets on egress ports in a network processing unit. In the context of this work, this scheduling should ensure that packets are sent in such a way to meet the allowed bandwidth quotas for each packet flow. Also, an important goal is to reduce latency to a minimum in order to best support the upcoming 5G wireless standards. The proposed hardware architecture of the systolic priority queue enables pipelined en/dequeue operations at constant time rate. Detailed description of this processing module is provided, together with the associated algorithm, and the architecture of the traffic manager. The implemented architecture is based on the C coding language and is synthesized with the Vivado High Level Synthesis tool. The obtained results are compared across a range of priority queue depths and performance metrics with existing approaches. A throughput improvement of 44% is claimed over best previously reported results. The proposed design of the traffic manager works at 118 MHz when implemented on a Kintex-7 FPGA from Xilinx.

Node configuration for the Aho-Corasick algorithm in Intrusion Detection Systems

In this paper, we analyze the performance and cost trade-off from selecting two representations of nodes when implementing the Aho-Corasick algorithm. This algorithm can be used for pattern matching in network-based intrusion detection systems such as Snort. Our analysis uses the Snort 2.9.7 rules set, which contains almost 26k patterns. Our methodology consists of code profiling and analysis, followed by the selection of a parameter to maximize a metric that combines clock cycles count and memory usage. The parameter determines which of two types of nodes is selected for each trie node. We show that it is possible to select the parameter to optimize the metric, which results in an improvement by up to 12× compared with the single node-type case.

P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs

Packet parsing is a key step in SDN-aware devices. Packet parsers in SDN networks need to be both reconfigurable and fast, to support the evolving network protocols and the increasing multi-gigabit data rates. The combination of packet processing languages with FPGAs seems to be the perfect match for these requirements. In this work, we develop an open-source FPGA-based configurable architecture for arbitrary packet parsing to be used in SDN networks. We generate low latency and high-speed streaming packet parsers directly from a packet processing program. Our architecture is pipelined and entirely modeled using templated \textttC++ classes. The pipeline layout is derived from a parser graph that corresponds to a P4 code after a series of graph transformation rounds. The RTL code is generated from the \textttC++ description using Xilinx Vivado HLS and synthesized with Xilinx Vivado. Our architecture achieves a \SI100 \giga\bit/\second data rate in a Xilinx Virtex-7 FPGA while reducing the latency by 45% and the LUT usage by 40% compared to the state-of-the-art.