Frank E. van Vliet

A Labeled Data Set for Flow-Based Intrusion Detection

Flow-based intrusion detection has recently become a promising security mechanism in high speed networks (1-10 Gbps). Despite the richness in contributions in this field, benchmarking of flow-based IDS is still an open issue. In this paper, we propose the first publicly available, labeled data set for flow-based intrusion detection. The data set aims to be realistic , i.e., representative of real traffic and complete from a labeling perspective. Our goal is to provide such enriched data set for tuning, training and evaluating ID systems. Our setup is based on a honeypot running widely deployed services and directly connected to the Internet, ensuring attack-exposure. The final data set consists of 14.2M flows and more than 98% of them has been labeled.

Unified Frequency-Domain Analysis of Switched-Series-

A wide variety of voltage mixers and samplers are implemented with similar circuits employing switches, resistors, and capacitors. Restrictions on duty cycle, bandwidth, or output frequency are commonly used to obtain an analytical expression for the response of these circuits. This paper derives unified expressions without these restrictions. To this end, the circuits are decomposed into a polyphase multipath combination of single-ended or differential switched-series-RC kernels. Linear periodically time-variant network theory is used to find the harmonic transfer functions of the kernels and the effect of polyphase multipath combining. From the resulting transfer functions, the conversion gain, output noise, and noise figure can be calculated for arbitrary duty cycle, bandwidth, and output frequency. Applied to a circuit, the equations provide a mathematical basis for a clear distinction between a “mixing” and a “sampling” operating region while also covering the design space “in between.” Circuit simulations and a comparison with mixers published in literature are performed to support the analysis.

RC

N-path filters exploiting switched-series-R-C networks can realize high-Q blocking-tolerant band-pass filters. Moreover, their center frequency is flexibly programmable by a digital clock. Unfortunately, the time variant nature of these circuits also results in unwanted signal folding. This paper proves analytically that folding can be reduced and band pass filtering can be improved by adding an inductance in series with the switched-R-C network. In contrast, a shunt capacitor degrades band-pass filter performance. The interaction between the reactive series impedance and the switched capacitors of an N-path filter complicates analysis due to memory effects associated with reactive components. Assuming N identical signal paths with 1/ N duty cycle, we show it is possible to solve the set of differential equations, by assuming that the signals in each path only differ in delay. Analytical equations are verified versus simulations, and the benefits in filter properties and reduction in signal folding are demonstrated.

Passive Mixers and Samplers

To reject strong interference in excess of 0 dBm, a 4- element LO-phase shifting phased-array receiver with 8-phase passive mixers terminated by baseband capacitors is presented. The passive mixers upconvert both the spatial and frequency domain filtering from baseband to RF, hence realizing blocker suppression directly at the antenna inputs. A comprehensive mathematical model provides a set of closed-form equations describing the spatial and frequency domain filtering including imperfections. A prototype is realized in 28 nm CMOS. It exploits third harmonic reception to achieve a wide RF-frequency range from 0.6-4.5 GHz at 34-119 mW power dissipation, while also providing impedance matching. Out of the band/beam, a 1 dB-compression point as high as +12/+10 dBm has been measured. The 1-element noise figure over the RF-frequency range is 4-6.3 dB, while in-beam/band IIP3 values of 0- +2.6 dBm are measured. This proposed technique can be instrumental to make RF receivers more robust for interference, while still being flexibly tunable in frequency.

Analysis of the Signal Transfer and Folding in N-Path Filters With a Series Inductance

This paper describes a 2-20 GHz 6-bit True-Time Delay. A total equivalent electrical length in air of 43.5 mm (145 ps) is achieved over a 2-20 GHz bandwidth. Digital drivers and a serial-to-parallel converter are integrated on the same MMIC. The ED02AH 0.2 ¿m PHEMT process from OMMIC is used. The time delay elements are realised using constant-R networks. The three smallest bits make use of a self-switched version of the constant-R networks while the 3 largest bits use a topology with single-pole double-throw (SPDT) switches and constant-R networks in the delay path. Measurement results for a typical chip are presented.

A 4-Element Phased-Array System With Simultaneous Spatial- and Frequency-Domain Filtering at the Antenna Inputs

At low-GHz frequencies, analog time-delay cells realized by LC delay lines or transmission lines are unpractical in CMOS, due to their large size. As an alternative, delays can be approximated by all-pass filters exploiting transconductors and capacitors (g m -C filters). This paper presents an easily cascadable compact g m -C all-pass filter cell for 1-2.5 GHz. Compared to previous g m -RC and g m -C filter cells, it achieves at least 5x larger frequency range for the same relative delay variation, while keeping gain variation within 1 dB. This paper derives design equations for the transfer function and several non-idealities. Circuit techniques to improve phase linearity and reduce delay variation over frequency, are also proposed. A 160 nm CMOS chip with maximum delay of 550 ps is demonstrated with monotonous delay steps of 13 ps (41 steps) and an RMS delay variation error of less than 10 ps over more than an octave in frequency (1-2.5 GHz). The delay per area is at least 50x more than for earlier chips. The all-pass cells are used to realize a four element timed-array receiver IC. Measurement results of the beam pattern demonstrate the wideband operation capability of the g m -RC time delay cell and timed-array IC-architecture.

A Wideband GAAS 6-Bit True-Time Delay MMIC Employing On-Chip Digital Drivers

Phased-array receivers provide two major benefits over single-antenna receivers [1]. Their signal-to-noise ratio (SNR) doubles for each doubling in the number of elements, resulting in extended range. Secondly, interferers can be rejected in the spatial domain for increased link robustness. These arrays can be implemented by phase shifting and summing the signals from antenna elements with uniform spacing. For accurate interference rejection, a phase shifter with uniform phase steps and constant amplitude is desired. Several types of continuous-time phase shifters have been published, e.g. using injection locking [2], phase selection [3] and vector modulation [1,4,5,6]. This paper proposes a phased-array receiver architecture with a discrete-time vector modulator that takes advantage of the high linearity and good matching of switched-capacitor circuits, which are highly compatible with advanced CMOS. A simple charge-redistribution circuit is presented that performs a rational approximation of the sine and cosine needed for the vector modulator weights.

Compact cascadable gm-C all-pass true time delay cell with reduced delay variation over frequency

Phased arrays in CMOS for consumer communication bands aim to enhance receiver performance by exploiting beamforming with antenna arrays. Sensitivity increases with the number of antenna elements through array gain and interferers can be cancelled through the spatial filtering of the beam pattern [1]. For the latter, the linearity of the receiver before the beamforming summing point becomes a bottleneck as interferers are not cancelled yet. Phase shifting in the LO domain reduces the complexity in the signal path and enables the use of linear signal blocks, but has high requirements on the multiphase LO generation [2]. On the other hand, a switched-capacitor phase shifter can be very linear, but is limited by the linearity of the necessary input matching and element summing gm-stages [3]. This paper proposes a fully passive phased-array receiver front-end which implements impedance matching, phase shifting and element summing with only switched-capacitor stages for a high linearity.

A 1.0-to-4.0GHz 65nm CMOS four-element beamforming receiver using a switched-capacitor vector modulator with approximate sine weighting via charge redistribution

Electronically variable delays for beamforming are generally realized by phase shifters. Although a constant phase shift can approximate a time delay in a limited frequency band, this does not hold for larger arrays that scan over wide angles and have a large instantaneous bandwidth. In this case true time delays are wanted to avoid effects such as beam-squinting. In this paper we aim at compactly integrating a delay based phased-array receiver in standard CMOS IC technology. This is for instance relevant for synthetic aperture radars, which require large instantaneous bandwidths often in excess of 1GHz, either as RF or as IF bandwidth in a superheterodyne system. We target low-GHz radar frequencies, assuming sub-arrays of four elements and up to 550ps delay.

A 1.5-to-5.0GHz input-matched +2dBm P 1dB all-passive switched-capacitor beamforming receiver front-end in 65nm CMOS

Beamforming phased-array receivers aim to increase receiver sensitivity and reject interferers in the spatial domain [1,2]. A receiver with programmable phase shift and high linearity is crucial to cope with interference. Switched-capacitor vector modulators can provide adequate phase shift and linearity [3,4], but so far, at the cost of a high power consumption. As power consumption increases linearly with the number of antenna elements, it is one of the bottlenecks hindering commercialization of beamforming. In this paper, we demonstrate several design techniques on architectural and circuit levels, to reduce the power consumption per element, while still achieving competitive Spurious Free Dynamic Range (SFDR).