Bram Nauta

A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time

A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a 1-sigma offset of 8mV, the circuit consumes 92fJ/decision with a 1.2V supply. It has an input equivalent noise of 1.5mV and requires 18ps setup-plus-hold time

Analog/rf solutions enabling compact full-duplex radios

In-band full-duplex sets challenging requirements for wireless communication radios, in particular their capability to prevent receiver sensitivity degradation due to self-interference (transmit signals leaking into its own receiver). Previously published self-interference rejection designs require bulky components and/or antenna structures. This paper addresses this form-factor issue. First, compact radio transceiver feasibility bottlenecks are identified analytically, and tradeoff equations in function of link budget parameters are presented. These derivations indicate that the main bottlenecks can be resolved by increasing the isolation in analog/RF. Therefore, two design ideas are proposed, which provide attractive analog/RF-isolation and allow integration in compact radios. The first design proposal targets compact radio devices, such as small-cell base stations and tablet computers, and combines a dual-port polarized antenna with a self-tunable cancellation circuit. The second design proposal targets even more compact radio devices such as smartphones and sensor network nodes. This design builds on a tunable electrical balance isolator/duplexer in combination with a single-port miniature antenna. The electrical balance circuit can be implemented for scaled CMOS technology, facilitating low cost and dense integration.

A robust 43-GHz VCO in CMOS for OC-768 SONET applications

In this paper, we present a 43-GHz LC-VCO in 0.13-/spl mu/m CMOS for use in SONET OC-768 optical networks. A tuned output buffer is used to provide 1.3 V/sub p-p/ (single-ended) into a 90-fF capacitive load as is required when the VCO is used in typical clock and data recovery (CDR) circuits. Phase noise is -90 dBc/Hz at a 1-MHz offset from the carrier; this meets SONET jitter specifications. The design has a tune range of 4.2%. The VCO, including output buffers, consumes 14 mA from a 1-V supply and occupies 0.06 mm/sup 2/ of die area. Modern CMOS process characteristics and the high center frequency of this design mean that the tank loss is not dominated by the integrated inductor, but rather by the tank capacitance. An area-efficient inductor design that does not require any optimization is used.

Lowering the SNR Wall for Energy Detection Using Cross-Correlation

Spectrum sensing is a key enabler of cognitive radio but generally suffers from what is called a signal-to-noise ratio (SNR) wall, i.e., a minimum SNR below which it is impossible to reliably detect a signal. For energy detection, which has the advantage of not requiring knowledge of the signal, the SNR wall is caused by uncertainty in the noise level. Cross-correlation has been suggested as a possible means to obtain higher sensitivity but has received little attention in the context of noise uncertainty. The idea of cross-correlation is to have two receive paths, where each path independently processes the signal before they are combined, such that the noise added to the input signal at the individual paths is largely uncorrelated. In this paper, we mathematically quantify the SNR wall for cross-correlation, showing that it linearly scales with the amount of noise correlation. This lower noise correlation results in higher sensitivity, which is significantly better than that for autocorrelation. Equations that can be used to estimate the benefit over autocorrelation and the measurement time for a required probability of detection and false alarm are derived.

A robust 43 GHz VCO in standard CMOS for OC-768 SONET applications

In this paper, we present a 43 GHz VCO in 0.13/spl mu/m CMOS for use in SONET OC-768 optical networks. The design has a large tune range of 4.2%, which is sufficient to hold the design center frequency over anticipated process spread and temperature variation. A tuned output buffer is used to provide 1.3 V/sub p-p/ (single-ended) into a 90 fF capacitive load as is required when the VCO is used in typical clock and data recovery (CDR) circuits. Phase noise is -90 dBc/Hz at a 1 MHz offset from the carrier; this meets SONET jitter specifications. The VCO, including output buffers, consumes 14 mA from a 1 V supply and occupies 0.06 mm/sup 2/ of die area.

An ultra low energy FSK receiver with in-band interference robustness exploiting a 3-Phase chirped LO

An ultra-low-energy Binary Frequency Shift Keying (BFSK) receiver is proposed. It features improved in-band interference tolerance by chirping the transmission frequency. To reduce the receiver power consumption, a novel three-phase passive mixer along with a three stage digitally controlled ring oscillator is proposed, while still allowing quadrature detection. A mixer-first direct conversion receiver architecture moves the required gain to lowest frequency and lowest bandwidth to reduce power consumption. A low power flip-flop based BFSK demodulator is proposed that reduces the baseband power further. The receiver is designed and fabricated in a 65 nm complementary metal-oxide-semiconductor process. It consumes 219 μW from 1.2 V power supply, while having a sensitivity of -70 dBm for a bit error rate of 0.1% at 2.4 GHz. Except the off-chip 64 MHz clock generation, the total receiver requires 27 pJ/bit. Using a chirped clock spreading of 360 MHz and chirp repetition rate of 1 MHz, it can tolerate up to -8 dB signal to interference ratio for all interferer frequencies. This is 13.5 dB better than previously reported in literature and 12 dB better than ideal noncoherent BFSK receiver interference robustness.