Frank Engel Rasmussen

Electroplating and characterization of cobalt-nickel-iron and nickel-iron for magnetic microsystems applications

The magnetic properties of pulse reverse (PR) electroplated CoNiFe and DC electroplated NiFe are presented. CoNiFe is a very promising material for magnetic microsystems due to the possibility of achieving a high saturation flux density (Bs) and a low coercivity (Hc). A new bath formulation has been developed, which by means of PR electroplating makes it possible to deposit high Bs CoNiFe with a low residual stress level. The magnetic properties have been determined using a new simple measurement setup that allows for wafer level characterization. The results have been validated by comparison to measurements performed with a vibrating sample magnetometer (VSM).

Fabrication of high aspect ratio through-wafer vias in CMOS wafers for 3-D packaging applications

A process for fabrication of through-wafer vias in CMOS wafers is presented. The process presented offers simple and well controlled fabrication of through-wafer vias using DRIE formation of wafer through-holes, low temperature deposition of through-hole insulation, doubled sided sputtering of Cr/Au, and electroless deposition of Cu. A novel characteristic of the process is the use of a metal etch stop layer providing perfect control of the etch profile of the wafer through-holes in combination with a remarkably improved etch uniformity across the wafer. Excellent through-hole insulation is provided through the use of a CVD deposited polymer, Parylene C, whereas electroless deposition of Cu ensures even distribution of the via metallization.

Deep Reactive Ion Etching for High Aspect Ratio Microelectromechanical Components

A deep reactive ion etch (DRIE) process for fabrication of high aspect ratio trenches has been developed. Trenches with aspect ratios exceeding 20 and vertical sidewalls with low roughness have been demonstrated. The process has successfully been used in the fabrication of silicononinsulator (SOI) released comb drive based resonators and tunable capacitors for MEMS applications. Brief characterizations of the devices are presented.

Batch fabrication of through-wafer vias in CMOS wafers for 3-D packaging applications

A technique for fabrication of through-wafer vias in silicon wafers containing complementq metal-oxide- semiconductor (CMOS) circuitry is presented. The application of the presented through-wafer vias with existing wafer level chip size packaging (WLCSP) technologies enables fabrication of very dense packages. The through-wafer vias are fabricated entirely by low temperature, CMOS compatible processes, thus designed to allow for post processing of vias in fully processed CMOS wafers. The fabrication of the presented through-wafer vias is based on KOH etching of wafer through-holes, low temperature deposition of dielectric material, and electrodeposition of photoresist and via metallization (Cu and Ni). A simple solution to the well-known CMOS compatibility issue of KOH is employed by protecting the front side of the CMOS wafer using a combmation of plasma enhanced chemical vapor deposited (PECVD) silicon nitride, sputter deposited TiW/Au and electroplated An. This protection scheme allows for batch processing of throngh- wafer vias. The fabricated through-wafer vias have a serial resistance of 40 mR and a parasitic capacitance to the Si substrate of 2.5 PF .

Batch processing of CMOS compatible feedthroughs

This paper presents a technique for batch fabrication of electrical feedthroughs in CMOS wafers. The presented process is designed with specific attention on industrial applicability. The electrical feedthoughs are processed entirely by low temperature, CMOS compatible processes. Hence, the process scheme allows for post processing of feedthroughs in any kind of fully processed CMOS wafer. The fabrication of the electrical feedthroughs is based on wet etching of through-holes, low temperature deposition of dielectric material, and electrodeposition of photoresist and feedthrough metal. The feedthrough technology employs a simple solution to the well-known CMOS compatibility issue of KOH by protecting the CMOS side of the wafer using sputter deposited TiW/Au. The fabricated feedthroughs exhibit excellent electrical performance having a serial resistance of 40 mΩ and a parasitic capacitance of 2.5 pF.