Matthias Heschel

Fabrication and characterization of truly 3-D diffuser/nozzle microstructures in silicon

We present microfabrication and characterization of truly three-dimensional (3-D) diffuser/nozzle structures in silicon. Chemical vapor deposition (CVD), reactive ion etching (RIE), and laser-assisted etching are used to etch flow chambers and diffuser/nozzle elements. The flow behavior of the fabricated elements and the dependence of diffuser/nozzle efficiency on structure geometry has been investigated. The large freedom of 3-D micromachining combined with rapid prototyping allows one to characterize and optimize diffuser/nozzle structures.

Conformal coating by photoresist of sharp corners of anisotropically etched through-holes in silicon

A new photoresist treatment is presented yielding conformal coating of three-dimensional silicon structures, including the sharp corners of through-holes obtained by anisotropic etching in (100)-silicon. Resist reflow from these corners is avoided by replacing the conventional baking procedure with a vacuum treatment. The investigated photoresist is Shipleys Eagle 2100 ED, a negative-working electrodepositable photoresist. Additionally, the vacuum treatment allows the photoresist to be used for lift-off processes. Electrical frontside to backside interconnections suitable for solder bonding have been realized applying the latter technique.

Fabrication of high aspect ratio through-wafer vias in CMOS wafers for 3-D packaging applications

A process for fabrication of through-wafer vias in CMOS wafers is presented. The process presented offers simple and well controlled fabrication of through-wafer vias using DRIE formation of wafer through-holes, low temperature deposition of through-hole insulation, doubled sided sputtering of Cr/Au, and electroless deposition of Cu. A novel characteristic of the process is the use of a metal etch stop layer providing perfect control of the etch profile of the wafer through-holes in combination with a remarkably improved etch uniformity across the wafer. Excellent through-hole insulation is provided through the use of a CVD deposited polymer, Parylene C, whereas electroless deposition of Cu ensures even distribution of the via metallization.

Laser direct etching of silicon on oxide for rapid prototyping

Structures have been etched in poly-silicon and amorphous silicon deposited on silicon oxide by laser direct writing. These patterns can be written with a high resolution and transferred to the underlying material via reactive ion etching. Three-dimensional structures can be obtained by multiple exposure of the silicon mask. Due to the fast turnaround time of direct writing processes, this technique can be applied for rapid prototyping of large-scale structures.

Chip-size-packaged silicon microphones

The first results of silicon microphones that are completely batch-packaged and integrated with signal conditioning circuitry in a chip stack are discussed. The chip stack is designed to be directly mounted into a system, such as a hearing instrument, without further single-chip handling or wire bonding. The devices are fully encapsulated and provided with a well-determined interface to the environment. The integrated microphones operate at a bias of 1.5 V and are expected to reach a sensitivity of 5 mV/Pa, an A-weighted equivalent input noise of 24 dB sound pressure level, and a power consumption of about 50 μW in the near future, thereby living up to the tight specifications of microphones for hearing instruments. Other potential applications include mobile phones, headsets, and wearable computers, in which space is constrained.

Batch fabrication of through-wafer vias in CMOS wafers for 3-D packaging applications

A technique for fabrication of through-wafer vias in silicon wafers containing complementq metal-oxide- semiconductor (CMOS) circuitry is presented. The application of the presented through-wafer vias with existing wafer level chip size packaging (WLCSP) technologies enables fabrication of very dense packages. The through-wafer vias are fabricated entirely by low temperature, CMOS compatible processes, thus designed to allow for post processing of vias in fully processed CMOS wafers. The fabrication of the presented through-wafer vias is based on KOH etching of wafer through-holes, low temperature deposition of dielectric material, and electrodeposition of photoresist and via metallization (Cu and Ni). A simple solution to the well-known CMOS compatibility issue of KOH is employed by protecting the front side of the CMOS wafer using a combmation of plasma enhanced chemical vapor deposited (PECVD) silicon nitride, sputter deposited TiW/Au and electroplated An. This protection scheme allows for batch processing of throngh- wafer vias. The fabricated through-wafer vias have a serial resistance of 40 mR and a parasitic capacitance to the Si substrate of 2.5 PF .

Silicon micro machined hermetic packaging technology for optical subassemblies

A novel technology for building hermetic optical subassemblies based on silicon is presented which supports precision alignment features, integration of passives, outstanding RF-performance and waferscale assembly and testing. Examples of OSAs will be shown

Batch processing of CMOS compatible feedthroughs

This paper presents a technique for batch fabrication of electrical feedthroughs in CMOS wafers. The presented process is designed with specific attention on industrial applicability. The electrical feedthoughs are processed entirely by low temperature, CMOS compatible processes. Hence, the process scheme allows for post processing of feedthroughs in any kind of fully processed CMOS wafer. The fabrication of the electrical feedthroughs is based on wet etching of through-holes, low temperature deposition of dielectric material, and electrodeposition of photoresist and feedthrough metal. The feedthrough technology employs a simple solution to the well-known CMOS compatibility issue of KOH by protecting the CMOS side of the wafer using sputter deposited TiW/Au. The fabricated feedthroughs exhibit excellent electrical performance having a serial resistance of 40 mΩ and a parasitic capacitance of 2.5 pF.

Processing and performance of broadband integrated resistor structures on non-planar topologies in hermetic silicon enclosure with vertical micro vias

We present the integration of thin film nickel-chromium (NiCr) resistors into a hermetic, 3D structured silicon packaging platform for wafer level sealing and demonstrate their performance as broadband passive components. Resistors on the cavity side walls can be designed by modeling the material deposition as a unidirectional flux

Multiple Through-wafer Interconnects for MEMS Applications

This chapter reports on the design and manufacturing of multiple through-wafer interconnects for stacking of microelectromechanical devices. The feedthroughs have been applied to an interconnect (intermediate) layer for an integrated microphone. The integrated microphone consists of the transducer part and an application specific integrated circuit (ASIC). The two parts are joined by stacking them on top of each other with the interconnect (intermediate) layer between them. The intermediate layer is a multifunctional layer. It provides the microphone with an acoustic frontchamber. The intermediate layer ensures the interchange of acoustical and electrical signals with the environment. Also, the intermediate layer protects the microphone during dicing, chip handling and in operation. The two active components are electrically connected through the intermediate layer by multiple wafer frontside to backside interconnects. The feedthrough interconnects are provided with under bump metallizations (UBM), solder bumps and sealing rings on the microphone side and top surface metallizations (TSM) on the ASIC side. The entire metallization system is based on electroplating techniques. The patterning of the metallizations has been done utilizing an electrodepositable photoresist (EDPR) as a plating mold. Several EDPR processes have been developed which are optimized for the respective metallization. The feedthrough interconnects have been optimized in terms of series resistance and parallel capacitance. Electrical characterization of the feedthrough interconnects has been carried out analytically and experimentally. The series resistance of one single interconnect wire is in the order of 100 mΩ. The parallel (parasitic) capacitance is in the order of 2 pF. Coupling between two adjacent feedthrough interconnects is negligible for low relative humidity ( 90%) the impedance between two wires may be reduced due to a condensed water film. Sensitivity measurements performed before and after bonding of the interconnect layer to the microphone showed identical results which proves sufficient (TΩ) isolation between the feedthrough wires.