Frank Ghenassia

Transaction Level Modeling

Transaction level modeling (TLM) is put forward as a promising solution above Register Transfer Level (RTL) in the SoC design flow. This chapter formalizes TLM abstractions to offer untimed and timed models to tackle SoC design activities ranging from early software development to architecture analysis and functional verification. The most rewarding benefit of TLM is the veritable hardware/software co-design founded on a unique reference, culminating in reduced time-to-market and comprehensive cross-team design methodology.

Using transactional level models in a SoC design flow

Embedded software accounts for more than half of the total development time of a system on a chip (SoC). The complexity of the hardware is becoming so high that the definition of the chip architecture and the verification of the implementation require new techniques. In this chapter we describe our proposed methodology for supporting these new challenges as an extension of the ASIC flow. Our main contribution is the identification and systematic usage in an industrial environment of an abstraction layer that describes SoC architecture to enable three critical activities: early software development, functional verification and architecture analysis. The models are also referred to as Transaction Level Models (TLM) because they rely on the concept of transactions to communicate. Examples of a multimedia platform and of an ARM subsystem highlight practical benefits of our approach.

Transaction Based Design: Another Buzzword or the Solution to a Design Problem?

Complex systems on chip (SoCs) present challenges in the design and verification process that cannot be adequately addressed by traditional methodologies based on register transfer descriptions. Some of the aspects are efficient design exploration based on component reuse, getting closure on the architecture, as well as early development, integration and verification of embedded software. In search for responses to these challenges, Transaction level modeling (TLM) has got quite some attention in the area of SoC design. This panel attempts to do a reality check on TLM from an engineering point of view. Questions to discuss are: Is the Transaction Level (TL) really useful for the design and/or for the verification of SoCs? How can TL speed up the design process and lowering the risk of design failures? What are the implications on tools, languages, and Intellectual Property (IP) used in the design/verification process? The panelists will share their thoughts on transaction based design and verification, and will discuss benefits and issues based on their experiences of applying transaction level methodologies.

SystemC and SystemVerilog: Where do they fit? Where are they going?

There is tremendous interest in design languages these days - and more particularly, SystemC and SystemVerilog. Sometimes the truth about design languages can be obscured by marketing and the press. This panel is meant to deepen the technical understanding of the DATE audience on the issue of design languages. It contains five technical experts - an academic expert in design languages and SystemC and SystemVerilog in particular; a language expert for each of SystemC and SystemVerilog; and a user expert for these two languages. The language experts have been heavily involved in the specification and evolution of their respective languages. The user experts have been heavily involved in developing use methodologies for these languages within their own design communities, and in applying them to real design problems. The panelists will consider the questions:what are the key capabilities of these languages and what do they offer to users?which design problems are they best used for? what is their scope?how has application of these languages to real design problems improved the productivity of designers and the quality of the design results?where should the languages develop further capabilities?

TLM: An Overview and Brief History

The trend of “the smaller the better” in semiconductor industry pictures a bright future for System-on-Chip (SoC). The full exploitation of new silicon capabilities, however, is limited by the tremendous SoC design complexity to be addressed within very short project schedule. This limiting factor has pushed the need for altering the classic SoC design flow into prominence. A novel SoC design flow starting from a higher abstraction level than RTL, i.e. System-to-RTL design flow, has surfaced as a real need in advanced SoC design teams. After a decade of attempts to define a useful intermediate abstraction between SoC paper specification and synthesizable RTL, the SystemC C++ open-source class library has finally emerged as the right vehicle to explore the adequate level of abstraction. Transaction Level Modeling (TLM), a methodology based upon such abstraction, has proven revolutionary values in bringing software and hardware teams together using the unique reference model; resulting in dramatic reduction of time-to-market and improvement of SoC design quality.

Bridging gap between simulation and spreadsheet study

System architects working on SoC design have traditionally been hampered by the lack of a cohesive methodology for architecture evaluation and co-verification of hardware and software. This paper focuses on a comprehensive analysis framework providing platform assembly facilities, system analysis tools, enhanced traffic model and SystemC TLM IP. This framework has been intensively used to design and analyze complex SOC Interconnect based on STBus protocol such as the one of 71xx families. By hiding the complexity of a simulation and filling the gap towards spreadsheet study and costly On-Chip analysis using traffic model, architects benefit from an easy access to an efficient simulation for performance evaluation.

A design automation roadmap for EUROPE (panel discussion)

Design automation in EUROPE needs to be revitalized through a more cooperative approach of problems and solutions. MEDEA has been instrumental in bringing cooperation between process and applications and showing weaknesses of design automation solutions with present players. A new burgeoning eclosion of start ups in strategic areas shows good promises in EUROPE. The goal is to launch new design solutions based on standard market tools complemented by new European start ups early offering in strategic areas. These design solutions will be dedicated to European needs but addressing global worldwide markets. The aim of this workshop is to debate on the MEDEA design automation roadmap as a European permanent forum for ideas exchanges and new strategic developments for the European industry .

A D&T Roundtable: Design automation in Europe

Electronic system design automation is becoming the enabling technology in several key domains, including the mobile telecommunications, consumer, and automotive industry segments. European authorities realize that leading-edge companies in these industries must develop strong research and development in system design to maintain their leading positions. This is why the authorities ore heavily funding cooperation between industries and universities through a 2,000-million-euro (US

Towards Bridging the Precision Gap between SoC Transactional and Cycle-Accurate Levels

2,200 million) prolect called MEDEA (MicroEIectronics Development for European Applications). The goal is to master new electronic system design automation technologies, including hardware-software codesign and mixed analog/digital systems. In this roundtable, representatives of academia, industry, and European organizations evaluate the existing technologies and predict their future. The roundtable was held last March at the internotionol conference on Design and Test in Europe (DATE99) in Munich. IEEE Design & Test thanks roundtable participants Joseph Borel (STMicroelectronics), Anton Souer (MEDEA Office), Wolfgang Rosenstiel (University of Tuebingen), Frank Ghenossio (STMicroelectronics), and Ernest0 Perea (STMicroelectronics) D&Tgrotefully acknowledges the help of Ahmed Jerraya (TIMA), and Soman Adham (LogicVision) and Adam Osseiron (Fluence), who helped organize the roundtable and acted as recorders.