Daniel D. Gajski

CEDAR: a large scale multiprocessor

This paper presents an overview of Cedar, a large scale multiprocessor being designed at the University of Illinois. This machine is designed to accommodate several thousand high performance processors which are capable of working together on a single job, or they can be partitioned into groups of processors where each group of one or more processors can work on separate jobs. Various aspects of the machine are described including the control methodology, communication network, optimizing compiler and plans for construction. 13 references.

Flow Graph Representation

Methodologies based on simple components, such as gate arrays and standard cells, are not adequate when designing complex VLSI systems. Silicon compilation, an evolutionary step from standard cell methodology, offers an increase in design complexity with an increase in design productivity. Silicon compilers can be broadly divided into structural, functional, and intelligent silicon compilers ([GajsSS]). In structural silicon compilation, the designer explicitly defines the microarchitecture; i.e. a structure consisting of registers, busses, RAMS and ALUs. Functional silicon compilers transform a behavioral description into a microarchitecture automatically.

Knowledge Based Control in Micro-Architecture Design

This paper describes the principles and implementation of design-process control in a micro-architecture compiler. The knowledge-base relies on both local and global evaluations to determine strategies to achieve global goals and then implements those strategies by manipulating hardware allocations and search heuristics. A system overview and annotated sample run are presented.

An Expert-System Paradigm for Design

level designer can become the detailed functional specification needed by a lower level. Within a design abstraction there are usually several possible alternative structures for a particular desired behavior. Each of these may exhibit differing cost performance characteristics and require different refinement and optimization techniques. These structures can be grouped into sets of similar characteristics called desrgn styles. Styles reflect varlous design approaches forced by different design constraints to achieve the same behavlor. A simple example Is the choice of ripple-carry addition versus carry-look-ahead. The ripple-carry adder is appropriate if space is at a higher premium than delay time. As each level is designed, constraints are produced which must be propagated to the designers at the lower levels. These constraints reflect design style declslons, or structural partitions of higher-level design constraints. Style decisions constrain the design styles and strategies of sub-section designers. An example is the decision to use pre-charged carry addition, forcing the use of appropriate implementation components. Structural partitioning refers to the dlvlding of global constraints such as time, power, or area into local constraints on these values. A requirement of 175nS as maximum cycle time makes demands on the critical path of operations in each cycle. As the design is implemented, this puts a partitioning constraint on the design of each functional component. Figure 1 shows the possible allocation of timing constraints in two stages of the design process. In the first case the allocation has simply divided the cycle time among the function units. In the second case (later in the design) a failure report from the multiply design task has forced a different allocation of time between the functional units. Iterative refinement of a design requires continuous performance monitoring relative to the design goals. This model assumes a simple approach similar to ‘Knobs’ and ‘Gauges’. A human operator monitoring a process closes the loop manually by reading the appropriate gauges and making adjustments to the knobs (parameters) controlling the process execution. We apply this same simple approach to controlling the design pro-

A parallel pipelined relational query processor

This paper presents the design of a relational query processor. The query processor consists of only four processing PIPEs and a number of random-access memory modules. Each PIPE processes tuples of relations in a bit-serial, tuple-parallel manner for each of the primitive database operations which comprise a complex relational query. The design of the query processor meets three major objectives: the query processor must be manufacturable using existing and near-term LSI (VLSI) technology; it must support in a uniform manner both the numeric and nonnumeric processing requirements a high-level user interface like SQL presents; and it must support the query-processing strategy derived in the query optimizer to satisfy certain system-wide performance optimality criteria.

Design of arithmetic elements for Burroughs Scientific Processor

The design criteria and implementation of the Arithmetic Element (AE) of the Burroughs Scientific Processor, a vector machine intended for scientific computation requiring speed of up to 50 million floating-point operations per second, is discussed. An array of 16 AEs operate in lockstep mode, executing the same instruction on 16 sets of data. The 16 AEs are one stage in a pipeline which consists of 17 memory modules, an input alignment network, and an output alignment network. The AE itself is not pipelined. It can perform over one hundred different operations including a floating-point addition, subtraction and multiplication, division, square root, among the others. Eight registers are provided for the storage of intermediate values and results. Modulo 3 residue arithmetic is used for checking hardware failures.

Decomposition of Logic Networks into Silicon

This paper describes a module compiler for decomposing arbitrary functional units of any complexity into abstract cells for customized VLSI layouts. The compiler takes the description of a functional unit as input and builds a dependence graph representation. The graph is then partitioned and the nodes are packed into abstract cell output descriptions. The algorithm will tailor the design to a given area and aspect ratio. Routing is done automatically through the cells.

Cell Compilation with Constraints

This paper describes a cell compiler that translates cell descriptions given in form of Boolean equations including pass transistors into layout descriptions in Caltech Intermediate Form (CIF). The translation process is constrained by given height and width of the cell and the position of each I/O signal on the boundary of the cell. Furthermore, the size of each transistor as well as power consumption can be arbitrarily chosen. This cell compiler allows routing through the cell in any direction. The cell architecture is based on PLA structures.

Automatic Design with Dependence Graphs

A design automation system for the design of digital systems from a high-level algorithmic description is proposed. The definition of the data-dependence graph and techniques for performing transformations that lead to optimization of hardware are described. The system can be used on several levels of design with the VLSI layout level given particular emphasis.

Silicon Compilers and Expert Systems for VLSI

The present VLSI design crisis was caused by advancements in VLSI technology which allow us to pack almost a million transistors on a single chip. The functional complexity of a chip has increased accordingly. First, this forced a chip designer, usually an experienced circuit designer, to become an expert in logic design, computer architecture, and application software. This requirement for accumulated expertise in one person and increased demand for new designs created a shortage of chip designers. Secondly, the design complexity prolonged the design cycle, which became almost as long as the lifetime of the product. To solve this design Crisis, an advancement in design methodology for VLSI technology is needed. Basically, there are three approaches. knowledse base of an expert system. The knowledge in the knowledge base can be divided basically into three categories: Concepts include basic terms of the problem domain (VLSI design in our case), which can be usually obtained from textbooks. Rules describe particular situations and desirable actions to be performed (design refinements in our case). This knowledge is based on experience, and is obtained from an expert. Strate