Frank Klefenz

Pattern Comparator Trigger (PACT) for the muon system of the CMS experiment

The general scheme for the fast, pipelined first level trigger on high pt muons in the CMS detector at LHC is presented. The prototype PACT system was tested in the high momentum muon beams in the RD5 experiment during 1993/94 runs. The obtained efficiency curves are shown.

Evaluating parallel architectures for two real-time applications with 100 kHz repetition rate (hadron collider data)

In the context of research and development activities for future hadron colliders, competitive implementations of real-time algorithms for feature extraction have been made on various forms of commercial pipelined and parallel architectures. The algorithms used for benchmarking serve for decision making and are of relative complexity; they are required to run with a repetition rate of 100 kHz on data sets of kilobyte size. Results are reported and discussed in detail. Among the commercially available architectures, pipelined image processing systems can compete with custom-designed architectures. General-purpose processors with systolic mesh connectivity can also be used. Massively parallel systems of the SIMD type (many processors executing the same program on different data) are less suitable in the presently marketed form. >

Programmable active memories in real-time tasks: implementing data-driven triggers for LHC experiments

The future Large Hadron Collider (LHC), to be built at CERN, presents among other technological challenges a formidable problem of real-time data analysis. At a primary event rate of 40 MHz, a multi-stage trigger system has to analyze data to decide which is the fraction of events that should be preserved on permanent storage for further analysis. We report on implementations of local algorithms for feature extraction as part of triggering, using the detectors of the proposed ATLAS experiment as a model. The algorithms were implemented for a decision frequency of 100 kHz, on different data-driven programmable devices based on structures of field- programmable gate arrays and memories. The implementations were demonstrated at full speed with emulated input, and were also integrated into a prototype detector running in a test beam at CERN, in June 1994.

Track recognition in 4 mu s by a systolic trigger processor using a parallel Hough transform

A parallel Hough transform processor has been developed that identifies circular particle tracks in a 2-D projection of the OPAL jet chamber. The system consists of a Hough transform processor that determines well-defined tracks, and a Euler processor that counts their number by applying the Euler relation to the threshold result of the Hough transform. A prototype of a systolic process has been built that handles one sector of the jet chamber. It consists of 35*32 processing elements that are loaded into 21 programmable gate arrays (XILINX). This processor runs at a clock rate of 40 MHz. It is tested offline with about 1000 original OPAL events. No deviations from the offline simulation are found. A trigger efficiency of 93% is obtained. The prototype, together with the associated drift time measurement unit, has been installed at the OPAL detector at the LEP (Large Electron Positron Collider) and 100 k events have been sampled to evaluate the system under detector conditions. >

A Systolic Hough Transform Processor as a Second Level Trigger for Drift Chambers

A systolic processor has been developed that executes a parallel Hough transform. The system has been tailored to a specific pattern recognition task, the identification of particle tracks in the r,φ projection of the OPAL jet chamber. For all well defined tracks the starting angle d the radius of curvature is computed in 3.3 μs. The system consists of a Hough transform processor that identifies the tracks and an Euler processor that counts their number by applying the Euler relation to the thresholded result of the Hough transform. For one sector of the detector a prototype system has been realized with 21 XILINX chips. It consists of 35×32 processing elements. The full scale system will use 26,880 processing elements. The processor can easily be adapted to different generalized Hough transforms and various detector geometries. The prototype has be n functionally tested with OPAL test data sets. No deviations from the offline simulation have been found. The prototype operates at a clock rate of 40 MHz.