Reinhard Männer

Calculating dense disparity maps from color stereo images, an efficient implementation

This paper presents an efficient implementation for correlation based stereo. Research in this area can roughly be divided in two classes: improving accuracy regardless of computing time and scene reconstruction in real-time. Algorithms achieving video frame rates must have strong limitations in image size and disparity search range, whereas high quality results often need several minutes per image pair. This paper tries to fill the gap, it provides instructions how to implement correlation based disparity calculation with high speed and reasonable quality that can be used in a wide range of applications or to provide an initial solution for more sophisticated methods. Left to right consistency checking and uniqueness validation are used to eliminate false matches. Optionally, a fast median filter can be applied to the results to further remove outliers. Source code will be made publicly available as contribution to the Open Source Computer Vision Library, further acceleration with SIMD instructions is planned for the near future.

Towards an Optimal Mutation Probability for Genetic Algorithms

In this paper the optimal parameter setting of Genetic Algorithms (GAs) is investigated. Particular attention has been paid to the dependence of the mutation probability P M upon two parameters, the dimension of the configuration space l and the population size M. Assuming strict conditions on both the problem to be optimized and the GA, P M converges to 0 as the population size M or the dimension of the configuration space l converges to infinity. For direct application a heuristic comprising these results is presented. The parameter settings obtained by applying this heuristic are in accordance with those which have been obtained earlier by experiment.

Multitasking on FPGA Coprocessors

Multitasking on an FPGA-based processor is one possibility to explore the efficacy of reconfigurable computing. Conventional computers and operating systems have demonstrated the many advantages of sharing computational hardware by several tasks over time. The ability to do run-time configuration and readback of FPGAs in a coprocessor architecture allows investigating the problems of implementing realistic multitasking. This paper explores the control software required to support task switching for an application split over the host processor - coprocessor boundary as well as the requirements and features of context saving and restoring in the FPGA coprocessor context. An FPGA coprocessor designed especially to support multitasking of such applications is described.

Using floating-point arithmetic on FPGAs to accelerate scientific N-Body simulations

This paper investigates the usage of floating-point arithmetic on FPGAs for N-Body simulation in natural science. The common aspect of these applications is the simple computing structure where forces between a particle and its surrounding particles are summed up. The role of reduced precision arithmetic is discussed, and our implementation of a floating-point arithmetic library with parameterized operators is presented. On the base of this library, implementation strategies of complex arithmetic units are discussed. Finally the realization of a fully pipelined pressure force calculation unit consisting of 60 floating-point operators with a resulting performance of 3.9 Gflops on an off the shelf FPGA is presented.

FPGA-based template matching using distance transforms

This paper presents a high-performance FPGA solution to generic shape-based object detection in images. The underlying detection method involves representing the target object by binary templates containing positional and directional edge information. A particular scene image is preprocessed by edge segmentation, edge cleaning and distance transforms. Matching involves correlating the templates with the distance-transformed scene image and determining the locations where the mismatch is below a certain user-defined threshold. Although successful in the past, a significant drawback of these matching methods has been their large computational cost when implemented on a sequential general-purpose processor. In this paper we present a step by step implementation of the components of such object detection systems, taking advantage of the data and logical parallelism opportunities offered by an FPGA architecture. The realization of a pipelined calculation of the preprocessing and correlation on FPGA is presented in detail.

VIRIM: a massively parallel processor for real-time volume visualization in medicine

Architecture and applications of a massively parallel processor are described. Volumes of 256×256×128 voxels can be visualized at a frame rate of 10 Hz using volume oriented visualization algorithms. A prototype of the scalable and modular system is currently set up. 3D rotation around an arbilrary rotation axis, perspective, zooming, and arbilrary gray value mapping are provided in real-time. Multiuser access over high-speed networks is possible. A volume oriented visualization algorithm is used that is tailored to the requirements in medicine [5]. With this algorithm, small structures of a size down to the pixel resolution, and structures without defined surfaces can be visualized as well as semitransparent objects. One application of the system is therapy planning in heart surgery.

Enable++: a second generation FPGA processor

In the computing community field, programmable processors are going to fill the niche for special purpose computing devices. A typical example is ultra fast pattern recognition in experimental particle physics, a task for which we constructed two years ago (1993), Enable 1, an FPGA processor rather specialized for pattern recognition algorithms in /spl mu/s domain, but also provided with modest features for coping with more general applications. The paper presents the follow up model Enable++, a 2nd generation FPGA processor that offers several substantial enhancements over the previous system for a wider range of applications: Enable++ is structured into three different state of the art modules for providing computing power, flexible and high speed I/O communication and powerful intermodule communication with a raw bandwidth of 3.2 GByte/s by an active backplane. The technical realization of all three modules is guided by the maximum usage of field programmable logic. The actual demand of computing and I/O power can be satisfied by the number of modules plugged into the crate. Enhanced features of Enable++ comprise the configurable processor topology provided by programmable crossbar switches. In combination with the 4/spl times/4 FPGA array and 12 MByte distributed RAM, the Enable++ computing core offers a strongly increased and scalable computing power. For building new applications, the system offers a comfortable programming and debugging environment consisting of a compiler for the C like hardware description language spC, a simulator and a source level debugger for hardware design.

Preemptive multitasking on FPGAs

In exploring the efficacy of reconfigurable computing, one of the dimensions is the possibility for multitasking on an FPGA-based processor. Conventional computers and operating systems have demonstrated the many advantages of sharing computational hardware by several tasks over time. The ability to do run-time configuration and readback of FPGAs in a coprocessor architecture enables exploration of the problems of implementing realistic multitasking.

Biomechanical Simulation of the Vitreous Humor in the Eye Using and Enhanced ChainMail Algorithm

The focus of this paper is the newly developed Enhanced ChainMail Algorithm that will be used for modeling the vitreous humor in the eye during surgical simulation. The simulator incorporates both visualization and biomechanical modeling of a vitrectomy, an intra-ocular surgical procedure for removing the vitreous humor. The Enhanced ChainMail algorithm extends the capabilities of an existing algorithm for modeling deformable tissue, 3D ChainMail, by enabling the modeling of inhomogeneous material. In this paper, we present the enhanced algorithm and demonstrate its capabilities in 2D.

MULTIPROCESSOR AND MEMORY ARCHITECTURE OF THE NEUROCOMPUTER SYNAPSE-1

A general purpose neurocomputer, SYNAPSE-1, which exhibits a multiprocessor and memory architecture is presented. It offers wide flexibility with respect to neural algorithms and a speed-up factor of several orders of magnitude--including learning. The computational power is provided by a 2-dimensional systolic array of neural signal processors. Since the weights are stored outside these NSPs, memory size and processing power can be adapted individually to the application needs. A neural algorithms programming language, embedded in C(+2) has been defined for the user to cope with the neurocomputer. In a benchmark test, the prototype of SYNAPSE-1 was 8000 times as fast as a standard workstation.