Frank M. L. van der Goes

A 1.5 mW 68 dB SNDR 80 Ms/s 2 × Interleaved Pipelined SAR ADC in 28 nm CMOS.

This paper presents a power-efficient 80 MS/s, 11 bit ENOB ADC. It is realized in 28 nm CMOS and is based on two interleaved pipelined SAR ADCs. It includes an on-chip reference generator and does not require any external components. The total power dissipation is 1.5 mW, resulting in a low-frequency Walden FOM of 9.1 fJ/conv-step and a low-frequency Schreier FOM of 172.2 dB, which is the largest FOM reported to date for sampling frequencies larger than 1 MS/s. The key aspects in achieving this excellent power efficiency include the choice of ADC architecture, integrator-based amplifiers used for noise filtering, the finite settling of the reference voltage during the SAR conversion, and the modified DAC switching scheme to reduce the DAC switching energy.

11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS

The resolution and sampling speed of recently reported SAR ADCs have increased to 11+ ENOB at 50 to 100MS/s [1,2]; however, power efficiency has unfortunately suffered when compared to lower-resolution, lower-speed ADCs. This design targets the same high speed and resolution while simultaneously achieving power efficiency previously associated only with low-speed, low-resolution ADCs. Furthermore, the power reported includes the consumption from the active reference generator, clock generator and encoder (since this is an industrial SoC), differentiating it from the majority of reported SAR ADCs. A dynamic residue amplifier with excellent noise-filtering properties, embedded in a pipelined architecture, is a key power-saving technique. In addition, an energy-efficient switched-capacitor (SC) DAC is obtained by using a small fraction of the total DAC capacitance during the initial SAR steps. The realized Walden FOM is 9.1fJ/conv-step while the Schreier FoM is 172.3dB, currently the highest reported number to date for sampling speeds greater than 0.1Ms/s, based on the extensive list of recent data converters compiled in [3].

A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration

A 12 bit pipeline ADC with residue amplifiers calibrated for gain and distortion is presented. The settling accuracy of the residue amplifiers was lowered to achieve higher energy efficiency and the resulting errors were corrected in multiple stages using a split-ADC calibration technique. Starting from a typical op amp implementation, the settling accuracy of the residue amplifier was relaxed by a factor of more than 3× in the first two stages and by 2× in the remaining stages. The ADC was implemented in 40 nm digital CMOS and shows a Schreier figure-of-merit of 157.5 dB at 1 V supply, sampling at 195 MS/s, with an SNDR/SFDR of 64.8 dB/82 dB. While working in continuous background mode, the split-ADC calibration improved the ADC SFDR by 37 dB within 70,000 samples.

8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS

The IEEE802.3an 10GBASE-T standard describes full-duplex 10Gb/s Ethernet transmission over four pairs of up to 100m UTP cable. For the implementation of high-density 10GBASE-T network switches, highly integrated transceivers are required that have both a small form factor and high power efficiency. This paper describes an analog front-end (AFE) that is used in a quad-port 10GBASE-T transceiver chip. The small form factor of the AFE allows for the use of a 23×23mm2 BGA package, enabling implementation of 48-port switches with all transceivers in a single row on the PCB pitch-matched to the RJ45 connector arrays. The design achieves >62dBc transmitter SFDR, >62dBc echo cancellation (EC) SFDR, and >60dBc receiver SFDR up to 400MHz. It occupies an area of 15.1mm2 per port in a 40nm CMOS process. At 100m full 10Gb/s traffic, the AFE dissipates less than 1.75W.

A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration

A 12-bit pipeline ADC with residue amplifiers calibrated for gain and distortion is presented. The settling accuracy of the residue amplifiers was lowered in order to achieve higher energy efficiency, and the resulting errors were corrected in multiple stages using a split-ADC calibration technique. Starting from a typical opamp implementation, the power consumption of the residue amplifier was reduced by roughly 70% in the first two stages and by 50% in the remaining stages. The ADC was implemented in 40nm digital CMOS and shows a Schreier figure-of-merit of 157.4 dB at 1V supply, sampling at 195MS/s, with an SNDR/SFDR of 64.77dB/82dB.

A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction

This paper proposes a class-AB residue amplifier topology that significantly improves the power efficiency of residue amplification. Due to its inherent high linearity, the amplifier can be allowed to have a reduced settling to further enhance its power efficiency while still maintaining the required linearity performance. Moreover, it enables an efficient way of correcting gain errors in the analog domain by simply tuning the bias current, without requiring any additional analog power. The digital power for calibration also becomes negligible, since the detection of gain errors can be done digitally at a slow rate. The calibration of the prototype pipelined split-ADC in a 40nm CMOS reaches convergence in only 12×103 clock cycles. The ADC achieves more than 10.3b ENOB near Nyquist input up to 106 MS/s clock speed. At 53 MS/s clock with close to Nyquist-frequency input, the ADC demonstrates an SNDR and SFDR of 66 dB and 77.3 dB respectively while consuming 9 mW of power, of which the residue amplifiers consume only 0.83 mW.

Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers

The speed of Ethernet over copper cables has steadily increased by a factor of 10,000 over the last four decades, from 1Mb/s in the earliest Ethernet implementations to 10Gb/s in recent systems. This paper describes the design considerations on all levels of the 10GBASE-T design hierarchy that form the basis for the implementation of highly power-efficient AFEs in full-duplex 10GBASE-T transceivers. It also shows how these considerations are implemented in a practical design. At frequencies up to 400MHz, the transceiver presented in this paper achieves >62dBc transmitter SFDR, >62dBc echo cancellation (EC) SFDR and >60dB receiver SFDR. Achieving a bit-error-rate (BER) better than 10-15, it dissipates less than 1.75W at full 10Gb/s traffic over a 100m cable, which is the lowest power for a 10GBASE-T AFE published to date.

A 12-bit 800 MS/s Dual-Residue Pipeline ADC

This paper presents the design of a pipeline analog-to-digital converter (ADC) based on the dual-residue principle. By applying this technique, the ADC becomes insensitive to the exact gain of the MDAC residue amplifiers. This allows these amplifiers to be designed with a relatively low open-loop gain and low bandwidth, which is favorable for the power consumption of the ADC. The offsets of the residue amplifiers, however, limit the accuracy of the ADC. Therefore, offset calibration is required for the ADC to achieve a high resolution.