Frank Slomka

Hardware/software codesign and rapid prototyping of embedded systems

The complexity and the short time to market of embedded systems require the use of automated techniques during the specification, implementation, and testing phases of such systems. Due to the cost requirements and the timing constraints of such systems, application-specific hardware solutions are often needed, making the codesign of hardware and software a major topic for the design automation of embedded systems. This article describes tools for the analysis, synthesis, and rapid prototyping of distributed embedded real-time systems and presents a complete design flow from specification to implementation.

An Annotational Extension of Message Sequence Charts to Support Performance Engineering

Publisher Summary This chapter describes the performance message sequence charts (PMSCs), an extension of message sequence chart (MSC)-96 to include performance aspects into the MSC language. The language extension allows for the cospecification of functional and performance aspects. This joint specification of functional and performance aspects eases the task of software engineers. PMSC supports the formal specification of a variety of aspects related to performance. This includes performance requirements, resource requirements, the specification of the available resources as well as the specification of the mapping of the MSC instances on the available resources. To support the use of tools based on MSC-96, the language extensions are embedded in comments of the original MSC-96 language. The cospecification based on MSC rather than on Specification and Description Language (SDL) supports the early evaluation of the performance of the system.

Generating mixing hardware/software systems from SDL specifications

A new approach for the translation of SDL specifications to a mixed hardware/software system is presented. Based on the computational model of communicating extended finite state machines (EFSM) the control flow is separated from data flow of the SDL process. Hence for the first time it is possible to generate a mixed hardware/software implementation of an SDL process. This technique also reduces the complexity for high-level and register-transfer synthesis tools for the hardware parts of the system. The advantage of this methodology is shown by a design example of a wireless communication chip.

Mixed abstraction level hardware synthesis from SDL for rapid prototyping

SDL is currently gaining interest as a system level specification language for HW/SW codesign. Automated synthesis of SDL in hardware so far had problems with its efficiency. The investigations on the resource usage of SDL-to-VHDL designs presented in this paper identify two key challenges: minimizing the overhead introduced by SDL process infrastructure, and choosing the appropriate synthesis method. This paper presents a framework for SDL hardware synthesis where VHDL code generation, high-level synthesis and RT-level synthesis are combined. A configurable run-time environment implements services like data handling and message passing in efficient, hand-coded library components, which take into account properties of the target architecture. For these components RT-level synthesis was found to be suitable. The behavior of each SDL process on the other hand is freely specified by the system designer. Depending on the type of application, i.e. complex data-oriented or control-oriented either high-level synthesis, RT-level synthesis, or a combination of both can prove to be optimal.

Schedulability analysis of heterogeneous systems for performance message sequence chart

Telecommunication systems are often specified in the standardized languages SDL and MSC. These languages allow only the specification of pure functional aspects. To remedy this problem we have combined the language MSC and performance aspects in Performance MSC (PMSC). From a PMSC specification a task model can be derived that includes beside computation times, periods and deadlines of tasks, also absolute start times of tasks and dependencies between task. This allows us to apply an extended schedulability analysis of asynchronous tasks on heterogeneous target architectures. We present the analysis technique and demonstrate with a small example, how the algorithm can be used for the real-time analysis of a cordless telephone.

A General Approach for the Specification of Real-Time Systems with SDL

In contrast to protocols of the network or transport layer the protocols for medium access have to consider the timing behavior of the communication medium. Although SDL is a widely used language for the specification of communication systems, in most cases time critical parts are not considered. In this paper, a design pattern is discussed that allows the specification of time critical functionality sucg as multiplexers or Quality-of-Service (QoS) schedulers. In many applications such services are running in a synchronous manner with the communication medium. A notation for timing aspects is needed for the specification of this behavior which itself is only possible in a sensible way with a formal model of time. Clocks are used to define the term real-time in a formal way, leading to the specification of timing constraints, for example sending data packets in deterministic time intervals within a communication system. In a case study from the mobile communication area, the design pattern was used to specify the MAC-Layer including time critical parts.

A scalable hardware library for the rapid prototyping of SDL specifications

A known problem in the area of hardware/software codesign is the selection of the proper interface between the different parts of the design. This paper presents a technique which eases the selection by combining different synthesis techniques together with rapid prototyping. The application field of the technique is the design of communication systems where C and VHDL are generated from a specification given in SDL. For the VHDL area, high-level synthesis is used to synthesize a behavioural description.

CORSAIR: HW/SW-Codesign von Kommunikationssystemen mit SDL

ZUSAMMENFASSUNG Der Artikel beschreibt die CORSAIR-Umgebung (Codesign and Rapid Prototyping System for Applications with Realtime Constraints) zum Entwurf und zur Implementierung von Kommunikationssystemen auf der Basis der formalen Beschreibungstechnik SDL. Im Unterschied zu gängigen SDL-Werkzeugen zielt das Projekt auf die Entwicklung gemischter HW/SW-Systeme anstatt reiner Softwareimplementierungen. Weitere Besonderheit unseres Ansatzes ist die durchgängige Berücksichtigung von Zeitanforderungen in allen Phasen des Entwicklungsprozesses. Unser Ansatz basiert auf einer Erweiterung von SDL, die die Beschreibung von Zeit- und Implementierungsaspekten unterstützt. CORSAIR zielt auf die weitgehende Automatisierung des Entwicklungsprozesses, entsprechend dem HW/SW-Codesign-Prinzip. HW/SW-Codesign unterstützt die späte und damit flexible Partitionierung der Spezifikation in Teile, die in Hardware bzw. in Software implementiert werden.