Richard Hofmann

Distributed performance monitoring: methods, tools, and applications

A method for analyzing the functional behavior and the performance of programs in distributed systems is presented. We use hybrid monitoring, a technique which combines advantages of both software monitoring and hardware monitoring. The paper contains a description of a hardware monitor and a software package (ZM4/SIMPLE) which make our concepts available to programmers, assisting them in debugging and tuning of their code. A short survey of related monitor systems highlights the distinguishing features of our implementation. As an application of our monitoring and evaluation system, the analysis of a parallel ray tracing program running on the SUPRENUM multiprocessor is described. It is shown that monitoring and modeling both rely on a common abstraction of a systems dynamic behavior and therefore can be integrated to one comprehensive methodology. This methodology is supported by a set of tools. >

Hardware/software codesign and rapid prototyping of embedded systems

The complexity and the short time to market of embedded systems require the use of automated techniques during the specification, implementation, and testing phases of such systems. Due to the cost requirements and the timing constraints of such systems, application-specific hardware solutions are often needed, making the codesign of hardware and software a major topic for the design automation of embedded systems. This article describes tools for the analysis, synthesis, and rapid prototyping of distributed embedded real-time systems and presents a complete design flow from specification to implementation.

Mixed abstraction level hardware synthesis from SDL for rapid prototyping

SDL is currently gaining interest as a system level specification language for HW/SW codesign. Automated synthesis of SDL in hardware so far had problems with its efficiency. The investigations on the resource usage of SDL-to-VHDL designs presented in this paper identify two key challenges: minimizing the overhead introduced by SDL process infrastructure, and choosing the appropriate synthesis method. This paper presents a framework for SDL hardware synthesis where VHDL code generation, high-level synthesis and RT-level synthesis are combined. A configurable run-time environment implements services like data handling and message passing in efficient, hand-coded library components, which take into account properties of the target architecture. For these components RT-level synthesis was found to be suitable. The behavior of each SDL process on the other hand is freely specified by the system designer. Depending on the type of application, i.e. complex data-oriented or control-oriented either high-level synthesis, RT-level synthesis, or a combination of both can prove to be optimal.

Monitoring program behaviour on SUPRENUM

It is often very difficult for programmers of parallel computers to understand how their parallel programs behave at execution time, because there is not enough insight into the interactions between concurrent activities in the parallel machine. Programmers do not only wish to obtain statistical information that can be supplied by profiling, for example. They need to have detailed knowledge about the functional behaviour of their programs. Considering performance aspects, they need timing information as well. Monitoring is a technique well suited to obtain information about both functional behaviour and timing. Global time information is essential for determining the chronological order of events on different nodes of a multiprocessor or of a distributed system, and for determining the duration of time intervals between events from different nodes. A major problem on multiprocessors is the absence of a global clock with high resolution. This problem can be overcome if a monitor system capable of supplying globally valid time stamps is used. In this paper, the behaviour and performance of a parallel program on the SUPRENUM multiprocessor is studied. The method used for gaining insight into the runtime behaviour of a parallel program is hybrid monitoring, a technique that combines advantages of both software monitoring and hardware monitoring. A novel interface makes it possible to measure program activities on SUPRENUM. The SUPRENUM system and the ZM4 hardware monitor are briefly described. The example program under study is a parallel ray tracer. We show that hybrid monitoring is an excellent method to provide programmers with valuable information for debugging and tuning of parallel programs.

A General Approach for the Specification of Real-Time Systems with SDL

In contrast to protocols of the network or transport layer the protocols for medium access have to consider the timing behavior of the communication medium. Although SDL is a widely used language for the specification of communication systems, in most cases time critical parts are not considered. In this paper, a design pattern is discussed that allows the specification of time critical functionality sucg as multiplexers or Quality-of-Service (QoS) schedulers. In many applications such services are running in a synchronous manner with the communication medium. A notation for timing aspects is needed for the specification of this behavior which itself is only possible in a sensible way with a formal model of time. Clocks are used to define the term real-time in a formal way, leading to the specification of timing constraints, for example sending data packets in deterministic time intervals within a communication system. In a case study from the mobile communication area, the design pattern was used to specify the MAC-Layer including time critical parts.

A prototyping system for high performance communication systems

Presents a prototyping platform for high-performance communication systems together with a design methodology. Based on a formal design entry and nonfunctional design goals such as execution time and overall system cost, a software/hardware partitioning is generated and its performance is estimated with formal models. Valid partitionings are then implemented on a prototyping platform which is based on a heterogeneous multiprocessor system and a reconfigurable FPGA board. Using model-based optimization and monitoring, each partitioning is evaluated and the results are fed back in the generation and estimation of new partitionings.

ZÄHLMONITOR 4: Ein Monitorsystem für das Hardware- und Hybrid-Monitoring von Multiprozessor- und Multicomputer-Systemen

Die Beobachtung (das Monitoring) der inneren Ablaufe in Multiprozessor- und Multicomputer-Systemen ist ein hervorragendes Werkzeug, um die Ursachen fur die extern festgestellte Gesamtleistung solcher Systeme zu analysieren und damit die Voraussetzungen fur eine Leistungsverbesserung zu schaffen. Im vorliegenden Papier wird ein Monitorsystem vorgestellt, das speziell fur (auch raumlich verteilte) Multiprozessor- und Multicomputer-Systeme entworfen wurde. Seine wesentlichen Eigenschaften sind die Kombination von verteilter und zentraler Instrumentierung des Objektsystems, die systemweite Ermittlung von Ereignisreihenfolgen und die quellbezogene Auswertung von Ereignisspuren. Neben dem globalen Konzept werden vertiefende Untersuchungen dargestellt, und es wird von ersten Meserfahrungen berichtet.

A general time model for the specification and design of embedded real-time systems

Design of complex embedded systems feasible with current and upcoming semiconductor technologies necessitates consideration of real-time from the beginning. However, the commonly used specification techniques do not consider temporal aspects in general like fulfillment of high level timing requirements or dynamic reactions on timing violations. In this paper, we discuss the restrictions of current specification techniques for embedded real-time systems and present a general time model that solves this issue. The time model contains the progress of time, the measurement of time and the specification of timing requirements based on event traces. In contrast to earlier techniques, preconditions determine the actual relevance of a specific timing bound. Exemplified for SDL, a solution for the specification of temporal aspects is shown. The advantages of this solution are discussed in a hardware/software co-design case study from the mobile communication area.

SIMPLE: a universal tool box for event trace analysis

The event trace analysis system SIMPLE allows the evaluation of arbitrarily formatted event traces. SIMPLE is designed as a software package which comprises independent tools that are all based on a new kind of event trace access: the trace format is described in a trace description language (TDL) and evaluation tools access the event trace through a standardized problem-oriented event trace interface (POET). The language TDL is designed for problem-oriented description of event traces. The POET library is a monitor-independent function interface which enables the user to access measured data stored in event trace files in a problem-oriented manner. In order to be able to access and decode differently structured measured data, POET uses the event trace description in TDL. The event trace access tool TDL/POET is designed in order to meet the following requirements: object system independence; monitor independence; and source reference.

A scalable hardware library for the rapid prototyping of SDL specifications

A known problem in the area of hardware/software codesign is the selection of the proper interface between the different parts of the design. This paper presents a technique which eases the selection by combining different synthesis techniques together with rapid prototyping. The application field of the technique is the design of communication systems where C and VHDL are generated from a specification given in SDL. For the VHDL area, high-level synthesis is used to synthesize a behavioural description.