Franz Hirler

A New Fast and Rugged 100 V Power MOSFET

A new, rugged 100 V power MOSFET of the OptiMOStrade 2-family is described. By applying compensation principles, a device technology was developed that combines low on-state resistance RON with outstanding switching properties. The technology also offers a small gate charge QG and a small gate resistance RG. In addition, the internal body diode, when acting as freewheeling diode, reveals a soft reverse-recovery with a small reverse-recovery charge Q RR. Therefore, the technology is particularly suitable for a variety of applications, including highly efficient DC-DC and AC-DC converters, telecommunication and server topologies, Class-D amplifiers, and motor control

Design of avalanche capability of Power MOSFETs by device simulation

The avalanche behavior of new 150 V trench power MOSFETs was designed with the help of two- dimensional device simulation techniques. The devices employ the compensation principle for low on-state losses. A new edge-termination structure ensures that avalanche breakdown always occurs in the cell region of the device. For the transistor cells, two different destruction regimes were identified: energy-related destruction and current-related destruction. Possible simulation approaches to account for the different effects were proposed. The found dependence on design parameters based on device simulation was qualitatively confirmed by experimental results. Furthermore, strong dependence between on-resistance and avalanche current was shown.

YFET - Trench superjunction process window extended

The drift zone of superjunction devices consists of compensated n- and p-columns. The manufacturability of such devices is based on the thorough control of acceptors and donator concentrations. Shrinking the cell pitch to a few micrometers requires considerably better compensation control compared to 10µm pitch devices. A new concept that applies a stack of Y-shaped field plates to a charge compensated device is investigated by numerical simulation. The YFET concept provides a 7 times larger compensation process window compared to a device with oxide filled trenches, allowing much higher doping concentrations. A specific on-resistance of 0.65Ωmm2 at a breakdown voltage of 680V can be achieved at a cell pitch of about 4.6µm.

Simulation of the failure mechanism of power DMOS transistors under avalanche stress

The failure mechanism caused by avalanche stress in power devices consisting of large DMOS cell arrays is investigated using electrothermal device simulation. To this end, we use the approximation of an infinitely large array, but allow for thermal interaction among the cells. The numerical analysis demonstrate the occurrence of unstable states, where a single hot spot and a current filament evolve in one particular ‘weak’ cell, thus confirming earlier work. We also demonstrate that the maximum temperature rise in the first cell exhibiting filamentary current flow can easily exceed the destructive level. Subsequent current and temperature redistributions observed in simulation thus turn out to be of no practical relevance.

A new robust power MOSFET family in the voltage range 80 V-150 V with superior low R/sub Dson/, excellent switching properties and improved body diode

A new 100-V power MOSFET of the OPTIMOSreg 2-family is described. The application of compensation principles leads to a device technology that combines low RON with outstanding switching properties. The technology also offers small gate charge QG and gate resistance RG. In addition, the internal body diode, if acting as free-wheeling diode, reveals a soft reverse recovery with a small reverse recovery charge QRR resulting in relatively small voltage overshoots. Therefore, the technology is particularly suitable for a variety of applications including highly efficient DC-DC and AC-DC converters, telecommunication and server topologies, as well as motor control