Freddy Balestro

Design of digital filters for advanced telecommunications ASIC's using a special-purpose silicon compiler

Complex DSP (digital signal processor) ASICs (application-specific integrated circuits) typically feature high-quality filters implemented as dedicated blocks. FIDYS (filter 1di synthesis system) is a new VLSI recursive filter compiler, specifically designed to meet those needs. It is fully integrated from behavioral frequency template specifications down to layout. It comprises a specific approximation and synthesis procedure, the generation of a systolic architecture with parameterized pipelining based on dedicated bit-serial operators, and final generation of a densely packed layout based on a minimal dedicated set of 1- mu m CMOS basic cells. A lossless discrete integrator ladder filter structure is used. It features an outstanding low sensitivity and a high degree of modularity and regularity that directly result in streamlined hardware and an efficient placement with minimal routing overhead. Examples of representative applications for telecommunications circuits are presented. >

Signal processing device using several different filterings, especially for audio-frequency coding of voice signals

The device comprises a first input (E1) and a first output (S1) which are capable respectively of receiving and delivering a plurality of analog signals and corresponding digital signals having different predetermined types of transmission specifications and associated with substantially homothetic predetermined elementary frequency attenuation templates. A second input (E2) and a second output (S2) are also provided, capable respectively of receiving and delivering a plurality of digital signals and corresponding analog signals having different predetermined types of transmission specifications, associated with different, substantially homothetic predetermined elementary frequency attenuation templates, as well as first and second signal conversion means arranged respectively between the first input and output and between the second input and output and including a single digital filter (6) in common, having a single frequency attenuation template which is compatible with all the elementary templates.

A chip set for 7 KHz handfree telephony

This paper presents three VLSI circuits developed for an enhanced quality handfree telephone terminal (bandwidth up to 7 KHz). A first circuit performs the intensive computation task required by an adaptive filter of up to 1020 taps at 16 kHz sampling frequency for acoustic echo cancellation (AEC). A microprogrammed DSP with a specific architecture implements the bit rate compression/expansion (IUT G722 recommendation) and controls the gain of the AEC. The third circuit performs AD and DA conversion with corresponding filtering at 16 Ksamples/s with 15 bits resolution. The three circuits have been designed in 1 /spl mu/ CMOS (AEC and analog front end) and 0,8 /spl mu/ CMOS technology (DSP). Measure results are also presented.<<ETX>>

A 3-V 0.5-/spl mu/m CMOS A/D audio processor for a microphone array

A 0.5-/spl mu/m 3-V CMOS mixed-mode audio processor is presented. It is mainly composed of 11 low-noise input channels and a dedicated digital audio processor. Analog input signals are provided through an 11-microphone array. The chip size is about 50 mm/sup 2/, and the power dissipation is less than 100 mW. This circuit is dedicated to multimedia applications.

Outils spécialisés de synthèse VLSI pour algorithmes de traitement numérique du signal

RésuméLa conception automatisée efficace de circuits complexes intégrant un système complet de traitement numérique du signal passe par ľutilisation de compilateurs de silicium spécialisés. Cet article présente trois outils individuellement adaptés à des types ďalgorithme et des gammes de débitv différentes et qui partent de spécifications de haut niveau pour en synthétiser directement une implantationvlsi basée sur une architecture cible fixée. Fidys et Genrif sont des générateursvlsi de filtres numériques, respectivement récursifldi en échelle etrif transversal, spécifiés au niveau comportemental sous forme de gabarit fréquentici. Ľarchitecture cible est isomorphe à la structure des filtres avec un opérateur matériel par opération. Fidys utilise une arithmétique bit-série pour des applications bas et moyens débits tandis que Genrif vise les hauts débits avec un chemin de données bit-parallèle. Cot s est un outil plus ambitieux qui ne restreint pas les fonctionnalités acceptées en entrée et met en -uvre toute spécification C sur une architecture cible de type chemin de données microprogrammable, optimisée en fonction de ľalgorithme compilé.AbstractSpecial-purpose silicon compilers are instrumental in making possible efficient implementations of complex digital signal processing systems on a single chip. This paper presents three such tools, each of them adapted to a specific kind of algorithm and throughput range, that generate the layout of avlsi block, based on a fixed target architecture, directly from its high-level specification. Fidys and Genrif respectively generate recursiveldi andfir vlsi digital filters, starting from behavioral frequency template specifications. The architecture is a direct one to one mapping from the filter structure. Fidys targets low-end and medium-range applications, using bit-serial architecture, whereas the bit-parallel architecture in Genrif is better adapted to high-end video applications. Cots is a more general-purpose tool that implements any C program on a customized microcoded datapath.