P. Senn

A switched-capacitor filter silicon compiler

Switched capacitor technique is one of the best methods for making integrated HOS filters, A lot of programs are now available to help the designer but they are not connected to each other, and therefore a more general tool, taking into account all the design steps is needed.

A 27-MHz digital-to-analog video processor

The authors describe a circuit intended for the restitution of a digital video signal into its analog red, green, and blue components. Sampling parameters according to CCIR recommendation 601 have been adopted for the digital interface. The circuit consists mainly of a complex digital processing part and three digital-to-analog converters. All of these functions have been implemented in a 38-mm/sup 2/ CMOS chip. The design goal was achieved by the development of an efficient 2- mu m CMOS technology dedicated to analog and digital applications. >

A video delay line compiler

A digital delay line compiler is described. Depending on the number of bits per word, the delay required, and the operating frequency, the compiler automatically generates the layout of the block, including output and input buffers and registers for synchronization. The implementation is independent of basic cell characteristics. The architecture is described, as well as the method used for area optimization. Experimental results are discussed.<<ETX>>

A 54-MHz CMOS programmable video signal processor for HDTV applications

A 54 MHz CMOS Video Processor with a systolic architecture suited for 2D symmetric FIR filtering will be reported. The circuit is a 1D digital filter comprised of a control part and an array of 8 Multiplication-Accumulation cells. This processor is capable of handling 32 equivalent multiply-add operations in a sampling period as short as 18 ns. Devices can be cascaded to increase the order of the filter in both dimensions, up to 1024 stages with no truncation errors. It has been developed in a 1.2 ¿m CMOS technology and it dissipates less than 500 mW at a 54 MHz clock frequency.

A low-power 8-b 1 3.5-MHz video CMOS ADC for visiophony ISDN applications

A half-flash, subranging, 8-b, 13.5-MHz, video ADC (analog-to-digital converter) using overlapped architecture that combines the advantages of both flash and half-flash converters is described. Its conversion rate is that of a flash, without any multiplexing and with a low number of comparators. Its low power consumption and the small silicon area required for its implementation enable it to be integrated in mixed digital/analog circuits such as a video acquisition circuit devoted to visiophony applications. It has been manufactured using a CMOS 1- mu m technology with two polysilicon and two metallization layers. >

A general purpose high speed equalizer

The circuit presented is a high-speed self-adaptive filter achieving equalization over a wide range of signals, with a frequency of up to 40.5 MHz, such as the European D2-MAC and HD-MAC transmission standards. This 105000-transistor chip has been designed in a CMOS 1.0- mu m technology and is being used in a D2-MAC reception environment. In addition to the cabled D2MAC environment, this circuit can be implemented in such applications such as HDTV (HDMAC via satellite transmission). Its frequency (up to 40.5 MHz) and its flexibility due to programmable parameters allow this chip to be integrated in a wide range of systems.<<ETX>>

A general-purpose high-speed equalizer

The circuit presented is a high-speed self-adaptive filter achieving equalization over a wide range of signals, with a frequency of up to 40.5 MHz, as for the European D2-MAC and high-definition multiplexed analog components (HD-MAC) transmission standards. The circuit is a self-adaptive 16-tap transversal filter achieving equalization on any 8-b coded signal. It contains periodically a window of binary or duobinary data samples, such as the D, D2, and HD-MAC signals. This chip includes a delay line of 240 8-b data samples which are used for the internal gradient computations. Only linear distortions (echos) can be corrected by this chip. This 105000-transistor chip has been designed in a CMOS 1.0- mu m technology and is being used in a D2-MAC reception environment. >

A 54 MHz chip set for HDTV filtering

The HDTV European project EUREKA-95 requires complex video processing to be carried out in the encoder. A chip set optimized for large kernel 2D transversal filters, including a programmable delay line and a filter chip, is presented. They can operate at 54 MHz and have been developed in a 1.0 mu m CMOS technology. The basic architecture is a modified transposed transversal filter systolic array, where an extra data bus and a 9-b adder are provided in each filter cell to handle the horizontal symmetry. Though expensive compared to a folded data bus, this structure can be pipelined to relax the timing demands for high-speed applications.<<ETX>>

A new multistage bandpass sigma-delta modulator

A new architecture for a multistage bandpass sigma-delta modulator which tolerates imperfections in the resonator function is proposed. The architecture involves using a FIR filter to reduce the non-cancellation of the quantization noise of the first stage resulting from circuit non-idealities. Computer simulations of two differents structures illustrate the superiority of the new architecture and confirm its ability to withstand reasonable circuit non-idealities.

A 54 MHz CMOS Programmable Video Signal Processor for HDTV Applications

A 54 MHz CMOS Video Processor with a systolic architecture suited for 2D symmetric FIR filtering will be reported. The circuit is a 1D digital filter comprised of a control part and an array of 8 Multiplication-Accumulation cells. This processor is capable of handling 32 equivalent multiply-add operations in a sampling period as short as 18 ns. Devices can be cascaded to increase the order of the filter in both dimensions, up to 1024 stages with no truncation errors. It has been developed in a 1.2 ?m CMOS technology and it dissipates less than 500 mW at a 54 MHz clock frequency.