Frederic Neuveux

A reconfigurable shared scan-in architecture

In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) architecture is defined. The composite architecture is created with analysis that relies on the compatibility relation of scan chains. Topological analysis and compatibility analysis are used to maximize gains in test data volume and test application time. The goal of the proposed synthesis procedure is to test all detectable faults in broadcast test mode using minimum scan-chain configurations. As a result, more aggressive sharing of scan inputs can be applied for test data volume and test application time reduction. The experimental results demonstrate the efficiency of the proposed architecture for real-industrial circuits.

Changing the scan enable during shift

This paper extends the reconfigurable shared scan-in architecture (RSSA) to provide additional ability to change values on the scan configuration signals (scan enable signals) during the scan operation on a per-shift basis. We show that the extra flexibility of reconfiguring the scan chains every shift cycle reduces the number of different configurations required by RSSA while keeping test coverage the same. In addition a simpler analysis can be used to construct the scan chains. This is the first paper of its kind that treats the scan enable signal as a test data signal during the scan operation of a test pattern. Results are presented on some ISCAS as well as industrial circuits.

Fully X-tolerant, very high scan compression

This paper presents a new X-blocking system which allows very high compression and full coverage even if the density of unknown values is very high and varies every shift. Despite the presence of Xs in scan cells, compression can be maximized by using PRPG and MISR structures. Results on industrial designs with various X densities demonstrate consistently high compression and full test coverage.

Integrating DFT in the physical synthesis flow

The industrys adoption of powerful design methodologies, such as physical synthesis, formal verification, and static timing analysis are speeding the implementation and verification of multi-million gate ASICs and systems-on-chip (SoC). As the design community moves to the complete adoption of a physical synthesis flow, it is becoming evident that test synthesis must be aware of layout issues and well integrated within physical design tools. By bringing in key physical functions into the front-end of the DFT/physical synthesis flow, the designer is able to successfully meet all design and testability goals, with minimum impact on timing closure. In this paper, we present a DFT synthesis flow tightly integrated within physical synthesis to achieve physically optimized scan designs. This flow describes new test technology which uses physical information to achieve optimal scan chain partitioning, timing-driven scan ordering and DFT driven placement to dramatically reduce routing congestion, and achieve a rapid and predictable timing closure.

Two-level compression through selective reseeding

As scan compression becomes ubiquitous, ever more complex designs require higher compression. This paper presents a novel, two-level compression system for scan input data generated by deterministic test generation. First, load care bits and X-control input data are encoded into PRPG seeds; next, seeds are selectively shared for further compression. The latter exploits the hierarchical nature of large designs with tens or hundreds of PRPGs. The system comprises a new architecture, which includes a simple instruction-decode unit, and new algorithms embedded into ATPG. Results on large industrial designs demonstrate significant data and cycle compression increases while maintaining test coverage and performance.

Test-model based hierarchical DFT synthesis

With increasing design sizes and adoption of System on a Chip (SoC) methodology, design synthesis and test automation tools are hitting capacity and performance bottlenecks. Currently, hierarchical synthesis flows for large designs lack complete designfor-test (DFT) support. With this paper, we address a solution, involving the introduction of test models in a traditional DFT synthesis flow, that we term Hierarchical DFT Synthesis (HDS). We discuss the use of Core Test Language (CTL) based test models combined with physical and timing models to provide a complete flow for chip-level DFT. In doing so we address some challenges the new flow presents such as Design Rule Checking (DRC), DFT architecting and optimization. We describe methods to overcome these challenges thereby presenting a new methodology to handle complex next generation designs.

Hybrid selector for high-X scan compression

Scan testing and scan compression are widely used, but ever more complex designs require higher compression, while the increased density of unknown (X) values reduces effective compression. In this paper, we present a new selector design which blocks all Xs while allowing more observability of non-X scan cells and which requires fewer input control values. Supported by novel test generation algorithms, the selector enables very high compression even if the density of unknown values is very high and varies every shift. Results on industrial designs with various X densities demonstrate consistently high compression and test coverage.