Frédéric Rousseau

An optimal memory allocation for application-specific multiprocessor system-on-chip

We present a novel and systematic approach for the design of shared memory architectures in the case of application-specific multiprocessor system-on-chip. This paper focuses on a memory allocation step which is based on an integer linear programming model. It permits one to obtain an optimal distributed shared memory architecture minimizing the global cost to access the shared data in the application, and the memory cost. Our approach allows automatic generation of an architecture-level specification of the application. The effectiveness of this approach is illustrated by a packet routing switch example.

Automatic generation of embedded memory wrapper for multiprocessor SoC

Embedded memory plays a critical role to improve performances of systems-on-chip (SoC). In this paper, we present a new methodology for embedded memory design in the case of application specific multiprocessor system-on-chip. This approach facilitates the integration of standard memory components. The concept of memory wrapper allows automatic adaptation of physical memory interfaces to a communication network that may have a different number of access ports. We give also a generic architecture to produce this memory wrapper. This approach has successfully been applied on a low-level image processing application.

Platform-based software design flow for heterogeneous MPSoC

Current multimedia applications demand complex heterogeneous multiprocessor architectures with specific communication infrastructure in order to achieve the required performances. Programming these architectures usually results in writing separate low-level code for the different processors (DSP, microcontroller), implying late global validation of the overall application with the hardware platform. We propose a platform-based software design flow able to efficiently use the resources of the architecture and allowing easy experimentation of several mappings of the application onto the platform resources. We use a high-level environment to capture both application and architecture initial representations. An executable software stack is generated automatically for each processor from the initial model. The software generation and validation is performed gradually corresponding to different software abstraction levels. Specific software development platforms (abstract models of the architecture) are generated and used to allow debugging of the different software components with explicit hardware-software interaction. We applied this approach on a multimedia platform, involving a high performance DSP and a RISC processor, to explore communication architecture and generate an efficient executable code for a multimedia application. Based on automatic tools, the proposed flow increases productivity and preserves design quality.

Fast and standalone Design Space Exploration for High-Level Synthesis under resource constraints

The very high computing capacity available in the latest Field Programmable Gate Array (FPGA) components allows to extend their application fields, in High-Performance Computing (HPC) as well as in embedded applications. This paper presents a new methodology for Design Space Exploration (DSE) in the context of High-Level Synthesis (HLS) for HPC and embedded systems targeting FPGAs. This new methodology provides very quickly an RTL description of the design under resources constraints. An autonomous flow is described, that performs incremental transformations of the input design description. The low complexity of the transformation evaluation, decision and exploration algorithms, associated with a greedy progression, makes this DSE methodology very fast. Moreover, this methodology respects a strict resource constraint given as bare FPGA primitive amounts. Hence, the generated design fits into the targeted FPGA or a partition of it. Such a methodology leads to autonomous, fast and transparent DSE, all these issues known to limit the use of HLS. Results on several benchmarks highlight the capabilities of our DSE methodology. The results show a high generation time speed-up compared to one other existing HLS approach, while preserving correct performance of the generated circuits.

Efficient Software Development Platforms for Multimedia Applications at Different Abstraction Levels

Multimedia applications require heterogeneous multiprocessor architectures with specific I/O components in order to achieve computation and communication performances. The different processors run different software stacks made of the application code and the hardware dependent software layer. Developing this software usually makes use of a high level programming environment that does not handle specific architecture capabilities. We propose abstract software development platforms allowing to debug incrementally the different software layers and able to accurately estimate the use of the resources of the architecture. The software development platform is an abstract model of the architecture allowing to execute the software with detailed hardware-software interaction, performance measurement and software debug. Different software development platforms are generated automatically from an initial Simulink model and are used to debug the different software components and to easily experiment with several mappings of the application onto the platform resources. In this paper we apply the proposed approach on a multimedia platform, involving a high performance DSP and a RISC processor, to validate the executable code for a MJPEG decoder application.

Adaptation of force-directed scheduling algorithm for hardware/software partitioning

An algorithm for the hardware/software partitioning problem is presented. In data flow systems, task scheduling modifies global characteristics and allows different implementation solutions. Our algorithm is based on assignment and scheduling algorithms which are well known in high-level synthesis. At each iteration, one task is scheduled if it involves the weakest constraints on the other tasks. Thus, the algorithm schedules all the tasks and gives implementation. This new algorithm is an adaptation of the force-directed scheduling algorithm with a cost function computation for hardware/software partitioning.

Service dependency graph: an efficient model for hardware/software interfaces modeling and generation for SoC design

Complex systems-on-chip are designed by interconnecting pre-designed hardware (HW) and software (SW) components. During the design cycle, a global model of the SoC may be composed of HW and SW models at different abstraction levels. Designing HW/SW interfaces to interconnect SoC components is a source of design bottlenecks. This paper describes a service-based model enabling systematic design and co-simulation of HW/SW interfaces for SoC design. This model, called Service dependency graph (SDG) allows modeling of complex and application-specific interfaces. We present also a model generator that can automatically build HW/SW interfaces based on service and resource requirements described by the SDG. This approach has been applied successfully on the design of an MPEG-4 encoder. Additionally the SDG seems to be an excellent intermediate representation for the design automation of HW/SW interfaces.

Automatic generation of component wrappers by composition of hardware library elements starting from communication service specification

A system-on-chip is composed of heterogeneous components interacting through a communication network. Wrappers are hardware components aimed to adapt these heterogeneous components to the network. Such an adaptation can be specified as a set of provided and required services, according to communication requirements and available resources. System-on-chip designers are required to quickly adapt to the fast changing system specifications, but the design of a wrapper can be time consuming. So this paper presents a new methodology for their automatic generation starting from a communication service specification. This specification, already used in the computer network community, is refined to an RTL model using a systematic library based approach. The effectiveness of the methodology is shown on an example.

Interface optimization during hardware-software partitioning

We present an approach allowing communication optimization during the hardware-software partitioning task. Our methodology focuses on systems represented by a dataflow graph whose nodes are elements of libraries. To abstract the communication constraints, we include communication nodes in this graph. Consequently assignment and scheduling of communications and operations can be determined together by the same partitioning algorithm. During partitioning, protocol optimization and bus scheduling are realized. We illustrate with a telecommunication system example the feasibility and the usefulness of our methodology.

EURETILE 2010-2012 summary: first three years of activity of the European Reference Tiled Experiment.

Abstract This is the summary of first three years of activity of the EURETILE FP7 project 247846. EURETILE investigates and implements brain-inspired and fault-tolerant foundational innovations to the system architecture of massively parallel tiled computer architectures and the corresponding programming paradigm. The execution targets are a many-tile HW platform, and a many-tile simulator. A set of SW process - HW tile mapping candidates is generated by the holistic SW tool-chain using a combination of analytic and bio-inspired methods. The Hardware dependent Software is then generated, providing OS services with maximum efficiency/minimal overhead. The many-tile simulator collects profiling data, closing the loop of the SW tool chain. Fine-grain parallelism inside processes is exploited by optimized intra-tile compilation techniques, but the project focus is above the level of the elementary tile. The elementary HW tile is a multi-processor, which includes a fault tolerant Distributed Network Processor (for inter-tile communication) and ASIP accelerators. Furthermore, EURETILE investigates and implements the innovations for equipping the elementary HW tile with high-bandwidth, low-latency brain-like inter-tile communication emulating 3 levels of connection hierarchy, namely neural columns, cortical areas and cortex, and develops a dedicated cortical simulation benchmark: DPSNN-STDP (Distributed Polychronous Spiking Neural Net with synaptic Spiking Time Dependent Plasticity). EURETILE leverages on the multi-tile HW paradigm and SW tool-chain developed by the FET-ACA SHAPES Integrated Project (2006-2009). The APE Parallel Computing Lab of INFN Roma is in charge of the EURETILE HW Design (QUonG system/APENet+ board/DNP (Distributed Network Processor) and Scientific Application Benchmarks. The Computer Engineering and Networks Laboratory (TIK) of ETH Zurich (Swiss Federal Institute of Technology) designs the high-level explicit parallel programming and automatic mapping tool (DOL/DAL) and a set of “Embedded Systems” benchmarks. The Software for Systems on Silicon (SSS) of the ISS institute of RWTH Aachen, investigates and provides the parallel simulation technology and scalable simulation-based profiling/debugging support. The TIMA Laboratory of the University Joseph Fourier in Grenoble explores and deploys the HdS (Hardware dependent Software) including the distributed OS architecture. TARGET Compiler Technologies, the Belgian leading provider of retargetable software tools and compilers for the design, programming, and verification of application-specific processors (ASIPs), is in charge of the HW/SW Co-design tools for custom components of the EURETILE architecture. Grant Agreement no. 247846 Call: FP7-ICT-2009-4 Objective FET-ICT-2009.8.1 Concurrent Tera-device Computing Scientific Coordinator: Pier Stanislao Paolucci, Istituto Nazionale di Fisica Nucleare, Roma, Italy Administrative Coordinator: Michela Giovagnoli, Istituto Nazionale di Fisica Nucleare, Roma, Italy