Frederick P. Herrmann

System design for pixel-parallel image processing

A system design for performing low-level image processing tasks in real time is presented. The design is based on large processor-per-pixel arrays implemented using integrated circuit technology. Two integrated circuit architectures are summarized: an associative parallel processor and a parallel processor employing DRAM cells. In both architectures, the layout pitch of one-bit-wide logic is matched to the pitch of memory cells to form high-density processing element arrays. The system design features an efficient control path implementation, providing high processing element array utilization without demanding complex controller hardware. Sequences of array instructions are generated by a host computer before processing begins, then stored in a simple controller. Once processing begins, the host computer initiates stored sequences to perform pixel-parallel operations. A programming framework implemented using the C++ programming language supports application development. A prototype system employs associative parallel processor devices, a controller, and the programming framework. Three sample applications, smoothing and segmentation, median filtering, and optical flow, establish the suitability of the system for real-time image processing.

A dynamic associative processor for machine vision applications

The use of massively parallel associative processors as coprocessors for accelerating machine vision applications is considered. They achieve very fine granularity, as every word of memory functions as a simple processing element. A dense, dynamic, content-addressable memory cell supports fully parallel operation, and pitch-matched word logic improves arithmetic performance with minimal area cost. An asynchronous reconfigurable mesh network handles interprocessor communication and image input/output, and an area-efficient pass-transistor circuit counts and prioritizes responders. Some applications are discussed.<<ETX>>

A 256-element associative parallel processor

A 256-element associative processing chip is designed for pixel-parallel image processing and machine vision applications. A five-transistor three-state dynamic memory cell is used, and each processing element has 64 trits of memory. Other processing element components include a function generator, an activity register, and connections to a reconfigurable mesh network and a response resolution subsystem. These are implemented with compact circuits designed within memory pitch constraints. The chip was fabricated in a double-poly CCD-CMOS process and characterized as fully functional. A sample image processing application is demonstrated on a four-chip prototype system. >

A dynamic three-state memory cell for high-density associative processors

A dynamic associative processor cell is described which stores three states (0, 1, and X) and performs read, match, and masked-write functions. Five MOS transistors are used, including two dual-gate structures available in MITs CCD/CMOS technology. The dual-gate CCD (charge coupled device) transistors are used to reduce the spooning current, which can discharge the storage node through the write transistors. Experimental results show the functionality of the cell and an acceptable degradation with continuous spooning

InAsSb/InAlAsSb quantum-well diode lasers emitting beyond 3 um

The current status of InAsSb/InAlAsSb quantum-well (QW) lasers emitting between 3 and 4 micrometer is described. QW lasers grown on GaSb substrates, with emission wavelengths at approximately 3.9 micrometer, have operated pulsed up to 165 K. At 80 K, cw power of 30 mW/facet has been obtained. Ridge-waveguide lasers have operated cw up to 128 K. QW lasers grown on InAs have emission wavelengths between 3.2 and 3.55 micrometer. Broad- stripe lasers have operated pulsed up to 225 K and ridge-waveguide lasers have operated cw to 175 K. Theoretical analysis of the laser gain using a 6 by 6 k (DOT) p model to calculate the valence subband structure is reported.

A 256-element Associative Parallel Processor

A 256-element associative processing chip is designed for pixel-parallel image processing and machine vision applications. A five-transistor three-state dynamic memory cell is used, and each processing element has 64 trits of memory. Other processing element components include a function generator, an activity register, and connections to a reconfigurable mesh network and a response resolution subsystem. These are implemented with compact circuits designed within memory pitch constraints. The chip was fabricated in a double-poly CCD-CMOS process and characterized as fully functional. A sample image processing application is demonstrated on a four-chip prototype system