Craig L. Keast

A wafer-scale 3-D circuit integration technology

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 times 1024 visible imager with an 8-mum pixel pitch, and a 64 times 64 Geiger-mode laser radar chip are described

Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

A 1024/spl times/1024 integrated image sensor with 8 /spl mu/m pixels, is developed with 3D fabrication in 150 mm wafer technology. Each pixel contains a 2 /spl mu/m/spl times/2 /spl mu/m/spl times/7.5 /spl mu/m 3D via to connect a deep depletion, 100% fill-factor photodiode layer to a fully depleted SOI CMOS readout circuit layer. Pixel operability exceeds 99.9%, and the detector has a dark current of <3 nA/cm/sup 2/ and pixel responsivity of /spl sim/9 /spl mu/V/e at room temperature.

Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip

Shows the feasibility of stacking SOI circuits to build 3D-ICs with dense vertical interconnects; the results are being applied to develop higher performance systems. Low-power circuits with three metal levels are fabricated with a 0.25/spl mu/m fully-depleted SOI technology. Three or more circuit layers are stacked and connected with 3D vias whose size, pitch, and resistance will be decreased by replacing the adhesive process with low temperature oxide bonding and utilizing tungsten plugs to fill high-aspect-ratio vias.

MEMS microswitches for reconfigurable microwave circuitry

The performance is reported for a new microelectromechanical structure (MEMS) cantilever microswitch. We report on both dc- and capacitively-contacted microswitches. The dc-contacted microswitches have contact resistance of less than 1 /spl Omega/, and the RF loss of the switch up to 40 GHz in the closed position is 0.1-0.2 dB. Capacitively-contacted switches have an impedance ratio of 141:1 from the open to closed state and in the closed position have a series capacitance of 1.2 pF. The capacitively-contacted switches have been measured up to 40 GHz with S/sub 22/ less than -0.7 dB across the 5-40 GHz band.

High-speed Schottky-barrier pMOSFET with f/sub T/=280 GHz

High-speed results on sub-30-nm gate length pMOSFETs with platinum silicide Schottky-barrier source and drain are reported. With inherently low series resistance and high drive current, these deeply scaled transistors are promising for high-speed analog applications. The fabrication process simplicity is compelling with no implants required. A sub-30-nm gate length pMOSFET exhibited a cutoff frequency of 280 GHz, which is the highest reported to date for a silicon MOS transistor. Off-state leakage current can be easily controlled by augmenting the Schottky barrier height with an optional blanket As implant. Using this approach, good digital performance was also demonstrated.

Engineering polycrystalline Ni films to improve thickness uniformity of the chemical-vapor-deposition-grown graphene films

It has been shown that few-layer graphene films can be grown by atmospheric chemical vapor deposition using deposited Ni thin films on SiO(2)/Si substrates. In this paper we report the correlation between the thickness variations of the graphene film with the grain size of the Ni film. Further investigations were carried out to increase the grain size of a polycrystalline nickel film. It was found that the minimization of the internal stress not only promotes the growth of the grains with (111) orientation in the Ni film, but it also increases their grain size. Different types of SiO(2) substrates also affect the grain size development. Based upon these observations, an annealing method was used to promote large grain growth while maintaining the continuity of the nickel film. Graphene films grown from Ni films with large versus small grains were compared for confirmation.

FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics

Ultralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design techniques, a complementary process technology is required to enable the highest performance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation at 0.3 V may achieve a 97% reduction in switching energy compared to conventional transistors. The process technology described in this article takes advantage of the capacitance and performance benefits of thin-body silicon-on-insulator devices, combined with a workfunction engineered mid-gap metal gate.

Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes with Two SOI Timing Circuit Layers

A 64times64 laser-radar (ladar) detector array with 50mum pixel size measures the arrival times of single photons using Geiger-mode avalanche photodiodes (APD). A 3-tier structure with active devices on each tier is used with 227 transistors, six 3D vias and an APD in each pixel. A 9b pseudorandom counter in the pixel measures time. Initial imagery shows 2ns time quantization

Power handling and linearity of MEM capacitive series switches

This paper presents the power handling and linearity of a capacitive series MEMS switch. The switching time as a function of incident RF power is also discussed. The MIT Lincoln Laboratory series capacitive MEMS switch handled nearly 10 Watts of RF power under cold switching conditions and up to 1.7 Watts of RF power under hot switching conditions. The power handling is a function of the pull-down voltage of the switch and the frequency of the RF signal.

Analog VLSI systems for image acquisition and fast early vision processing

This article describes a project to design and build prototype analog early vision systems that are remarkably low-power, small, and fast. Three chips are described in detail. A continuous-time CMOS imager and processor chip uses a fully parallel 2-D resistive grid to find an objects position and orientation at 5000 frames/second, using only 30 milliwatts of power. A CMOS/CCD imager and processor chip does high-speed image smoothing and segmentation in a clocked, fully parallel 2-D array. And a chip that merges imperfect depth and slope data to produce an accurate depth map is under development in switched-capacitor CMOS technology.