Frederick T. Brady

Hot-Carrier Reliability of Fully Depleted Accumulation Mode Soi Mosfets

The accumulation mode devices used in this experiment were presented in detail in a previous paper [2]. They were made in a 0.5pm CMOS on SO1 technology, with a lOOnm thick silicon, 12.5nm gate oxide and a reverse gate type compared to the source/drain doping. For purpose of comparison, enhancement mode devices made in a similar CMOS technology were used. Figure 1 shows the output characteristics of Lmask70.8pm (a) n- and (b) pchannel MOSFET. The accumulation devices show a reduced effect of impact ionization close to the drain, which allows them to operate at higher drain voltages [a]. Because of this reduced drain electric field, hot-carrier reliability of accumulation mode MOSFETs is improved, as shown in figure 2 for the case of the n-channel MOSFET. In both devices the maximum degradation occurs close to the threshold voltage, contrary to the case of the bulk device, where the maximum degradation occurs at a point of maximum substrate current. The strong degradation at VG close to V, is due to the hot-hole injection close to the avalanche breakdown of the drain junction [3]. Since the breakdown voltage decreases when the gate voltage increases, as can be seen on figure 2, hot-carrier generation and its effects are also reduced. Figure 3 shows that enhancement mode pchannel devices have a better reliability than accumulation mode devices, in spite of the fact that both types of devices were stressed at the same peak gate current (fig. 3). In both devices the drain current and the threshold voltage vary similarly, indicating that the degradation mechanism are similar. Figure 4 details the variation of the subthreshold characteristics of the accumulation mode device. The I,(VG) characteristics is shifted due to electron trapping, and the short channel behavior of the device is degraded (the difference between the characteristics at high and low drain voltage is increased after stress). This and the increase of the drain current in strong inversion (fig. 4) indicate that the device is shortened, due to electron trapping, similarly to the case of bulk pchannel MOSFETs. The increased degradation of the accumulation mode device is due to the degraded short-channel behavior of accumulation mode devices, which was already observed in bulk p-channel buried channel devices [4]. However, the accumulation mode device requires a higher drain voltage than the enhancement mode devices -at a given gate current, so that at a given drain voltage it’s reliability is still comparable to that of an enhancement mode device. Furthermore, at drain voltages comparable to those in the n-channel MOSFET, the degradation of the pchannel device is negligible, so that the overall reliability of an accumulation mode CMOS circuit is not affected by the increased degradation of the p-channel device.

Manufacturability considerations for fully depleted SOI

Performance advantages of SOI technology have been widely published. However, a critical step in the maturation of any technology is progressing from demonstrating best case performance advantages to demonstrating repeatable performance. For a technology to be production qualified, target values must be met for critical parameters, with lot parametric variations within the required tolerances. We examine fully depleted SOI from this point of view. As a result of the very thin Si films used in fully-depleted SOI, sensitivities are found for process steps such as oxidation, salicide formation, and photolithography that are not found in bulk silicon or partially-depleted SOI. Since one of most important SOI substrate parameters is the thickness of the Si film (tsi), we focus here on how key electrical parameters are affected by tsi, for both mean and standard deviation. We find that not only is the tsi variation across a single wafer important, but that it must be controlled lot to lot. This impacts SOI wafer suppliers, as well as VLSI production flows in which sacrificial oxidations are done.<<ETX>>