Nadim F. Haddad

Enhanced performance of accumulation mode 0.5 mu m CMOS/SOI operated at 300 K and 85 K

A 0.5 mu m fully depleted CMOS on thin SOI (silicon-on-insulator) VLSI technology has been developed for SRAM and logic applications. Using a normally off, accumulation mode SOI device design with the source/drain/substrate having the same doping polarity, the device transconductance, mobility, and gate delay are improved by 40% over conventional enhancement mode devices. By cooling the devices to liquid nitrogen temperature, both n- and p-channel devices show improvement in mobility and transconductance, reduction of subthreshold slopes, and an increase of breakdown voltages from the floating substrates.<<ETX>>

Effects of iron contamination of thin oxide breakdown and reliability characteristics

The effect of iron contamination in silicon on the properties of thermally grown thin oxides is studied through electrical modeling and experimental MOSDOT testing. Iron concentration is measured using a surface photovoltage diffusion length measurement technique. Failure mechanisms related to iron contamination are proposed. Contamination limits for various gate oxide thicknesses are defined. Experimental results show that reduction of oxide thickness from 20 nm to 10 nm requires a reduction in iron contamination by 100 times.<<ETX>>

Considerations for the development of radiation resistant devices and VLSI circuits

The impact of radiation on Very Large Scale Integration (VLSI) silicon technology is discussed with a focus on Complimentary Metal-Oxide Semiconductor (CMOS). Effects of total dose, transient radiation, single event phenomena, and neutron fluence on devices and circuits are presented. General approaches to mitigating radiation effects are put forth. With proper considerations, VLSI CMOS can be enhanced to achieve several orders-of-magnitude increase in radiation tolerance.

Monitoring Iron Contamination in Silicon by Surface Photovoltage and Correlation to Gate Oxide Integrity

The effects of iron contamination on gate oxide characteristics are examined from an experimental and modeling perspective. Gate oxide integrity is measured for silicon wafers contaminated with 10 10 to 10 14 cm −3 of iron. Thermal oxides of 8, 10,13 and 20nm are studied. Iron concentration in silicon is measured non-destructively using Surface Photovoltage (SPV) minority carrier lifetime analysis. The SPV analysis technique is described. Based on the experimental data, allowable threshold iron contamination levels for various gate oxide thicknesses are established. For 10nm oxides, iron concentration cannot exceed 8×10 10 cm −3 without severe degradation in oxide quality. The threshold contamination level for 20nm oxides is 200 times higher. Time dependent dielectric breakdown (TDDB) test results indicate detrimental reliability effects can occur at even lower contamination levels.