Fredrik Kristensen

Background segmentation beyond RGB

To efficiently classify and track video objects in a surveillance application, it is essential to reduce the amount of streaming data. One solution is to segment the video into background, i.e. stationary objects, and foreground, i.e. moving objects, and then discard the background. One such motion segmentation algorithm that has proven reliable is the Stauffer and Grimson algorithm. This paper investigates how different color spaces affect the segmentation result in terms of noise and shadow sensitivity. Shadows are especially problematic since they not only distort shape but can also result in falsely connected objects that will complicate tracking and classification. Therefore, a new decision kernel for the segmentation algorithm is presented. This kernel alters the probability of foreground detection to reduce shadows and to increase the chance of correct segmentation for objects with a skin tone color, e.g. faces.

Real-Time Extraction of Maximally Stable Extremal Regions on an FPGA

This paper describes the implementation of a realtime maximally stable extremal region (MSER) detector. In order to reach real-time performance, both algorithmic and memory issues have been addressed. The union-find algorithm, which is the heart of the MSER detector, is extended to create linked regions that significantly decrease the time to extract MSERs. Hash indexed memory structures are used to locate stored regions fast while keeping the amount of stored data low. The design is verified by including it in a demonstrator circuit. Timing and memory requirements are presented for the demonstrator and as a function of image resolution

A low complexity architecture for binary image erosion and dilation using structuring element decomposition

This paper describes a new hardware architecture for binary image erosion and dilation. The design is to be used in a self contained real-time surveillance system. Thus, low complexity and low power consumption are main constraints. To achieve this goal the aim has been to reduce memory requirements and the number of memory accesses per pixel. By storing only the number of consecutive ones that appears horizontally and vertically in the input image, only two internal memory accesses per calculated output pixel are required. The number of memory accesses is independent of the size of the structuring element (SE) as long as it is rectangular and only contains ones, which is a common case. The internal memory size is proportional to log/sub 2/(SE/sub height/), which means that a large span of SE sizes can be supported with a small amount of hardware.

Low-Complexity Binary Morphology Architectures With Flat Rectangular Structuring Elements

This article describes and evaluates algorithms and their hardware architectures for binary morphological erosion and dilation. In particular, a fast stall-free low-complexity architecture is proposed that takes advantage of the morphological duality principle and structuring element (SE) decomposition. The design is intended to be used as a hardware accelerator in real-time embedded processing applications. Hence, the aim is to minimize the number of operations, memory requirement, and memory accesses per pixel. The main advantage of the proposed architecture is that for the common class of flat and rectangular SEs, complexity and number of memory accesses per pixel is low and independent of both image and SE size. The proposed design is compared to the more common delay-line architecture in terms of complexity, memory requirements and execution time, both for an actual implementation and as a function of image resolution and SE size. The architecture is implemented for the UMC 0.13- mum CMOS process using a resolution of 640 × 480. A maximum SE of 63 × 63 is supported at an estimated clock frequency of 333 MHz.

Implementation of a Labeling Algorithm based on Contour Tracing with Feature Extraction

This paper describes an architecture of a connected-cluster labeling algorithm for binary images based on contour tracing with feature extraction. The implementation is intended as a hardware accelerator in a self contained real-time digital surveillance system. The algorithm has lower memory requirements compared to other labeling techniques and can guarantee labeling of a predefined number of clusters independent of their shape. In addition, features especially important in this particular application are extracted during the contour tracing with little increase in hardware complexity. The implementation is verified on an FPGA in an embedded system environment with an image resolution of 320 times 240 at a frame rate of 25 fps. The implementation supports labeling of 61 independent clusters, extracting their location, size and center of gravity.

Teaching digital ASIC design to students with heterogeneous previous knowledge

This paper describes an MSc level digital ASIC project course. The majority of the course participants are international students, having a wide spread in previous knowledge in the field of digital HW-design. A course outline adapting to this fact has been developed, changing from one joint VLSI project towards smaller individual projects. The diversity in previous knowledge is evened out by adding lectures regarding design methodology and used EDA-tools, and making the first part of the course purely laboratory. To enhance and highlight different aspects of HDL-design, mandatory assignments allow the students to gradually take command over the complete design flow. As a result, comprehension of digital ASIC design is increased among the students and course administration is reduced.

Reduced transceiver-delay for OFDM systems

In this paper, it is shown that more than half of the data flow buffer, due to a bit reversed FFT output and cyclic prefix in an OFDM transceiver, can be removed. To achieve this, a new pipelined FFT processor is proposed and a cyclic suffix is used instead of the more commonly used cyclic prefix. The FFT processor is used either with a forward or backward data flow, i.e. performing either a decimation in time or a decimation in frequency FFT. However, this approach precludes wordlength optimization in the processor and therefore a semi floating-point arithmetic is used to achieve high signal-to-noise ratio. Total delay through the transceiver is reduced by 25% and for larger transceivers silicon area is reduced by as much as 25%. In addition, the proposed scheme reduces the required amount of memory accesses to insert a cyclic extension, and has the basic properties of a simple interleaver.

A generic transmitter for wireless OFDM systems

To fully utilize the available spectrum for a wireless communication system it is feasible to adapt to different situations on the channel as well as different systems with various quality of service. In this paper a generic OFDM transmitter is presented and it is shown that high flexibility can be obtained with a reasonable amount of additional hardware. Part of the design, the FFT-processor, has already been fabricated and measurement results are presented.

Low complexity real-time feature extraction, using image projections

In this paper it is shown how low complexity image projections can be used to replace the much more memory demanding functions morphology and labeling. The image projections are intended to be used in an automatic real-time surveillance system to detect objects and extract features. The projection unit operates directly on the binary motion mask from the segmentation unit and can extract location, size and center of gravity of the detected objects. To increase the precision, multiple projections are calculated in the Y-direction of the motion mask. To verify the design a demonstrator has been implemented on a Xilinx FPGA, where the effect of different input settings can be evaluated in real-time. Compared to the previous solution with morphology and labeling, the memory requirement is reduced from O(n 2) to O(n).