Hugo Hedberg

A low complexity architecture for binary image erosion and dilation using structuring element decomposition

This paper describes a new hardware architecture for binary image erosion and dilation. The design is to be used in a self contained real-time surveillance system. Thus, low complexity and low power consumption are main constraints. To achieve this goal the aim has been to reduce memory requirements and the number of memory accesses per pixel. By storing only the number of consecutive ones that appears horizontally and vertically in the input image, only two internal memory accesses per calculated output pixel are required. The number of memory accesses is independent of the size of the structuring element (SE) as long as it is rectangular and only contains ones, which is a common case. The internal memory size is proportional to log/sub 2/(SE/sub height/), which means that a large span of SE sizes can be supported with a small amount of hardware.

Binary Morphology With Spatially Variant Structuring Elements: Algorithm and Architecture

Mathematical morphology with spatially variant structuring elements outperforms translation-invariant structuring elements in various applications and has been studied in the literature over the years. However, supporting a variable structuring element shape imposes an overwhelming computational complexity, dramatically increasing with the size of the structuring element. Limiting the supported class of structuring elements to rectangles has allowed for a fast algorithm to be developed, which is efficient in terms of number of operations per pixel, has a low memory requirement, and a low latency. These properties make this algorithm useful in both software and hardware implementations, not only for spatially variant, but also translation-invariant morphology. This paper also presents a dedicated hardware architecture intended to be used as an accelerator in embedded system applications, with corresponding implementation results when targeted for both field programmable gate arrays and application specific integrated circuits.

Low-Complexity Binary Morphology Architectures With Flat Rectangular Structuring Elements

This article describes and evaluates algorithms and their hardware architectures for binary morphological erosion and dilation. In particular, a fast stall-free low-complexity architecture is proposed that takes advantage of the morphological duality principle and structuring element (SE) decomposition. The design is intended to be used as a hardware accelerator in real-time embedded processing applications. Hence, the aim is to minimize the number of operations, memory requirement, and memory accesses per pixel. The main advantage of the proposed architecture is that for the common class of flat and rectangular SEs, complexity and number of memory accesses per pixel is low and independent of both image and SE size. The proposed design is compared to the more common delay-line architecture in terms of complexity, memory requirements and execution time, both for an actual implementation and as a function of image resolution and SE size. The architecture is implemented for the UMC 0.13- mum CMOS process using a resolution of 640 × 480. A maximum SE of 63 × 63 is supported at an estimated clock frequency of 333 MHz.

Implementation of a Labeling Algorithm based on Contour Tracing with Feature Extraction

This paper describes an architecture of a connected-cluster labeling algorithm for binary images based on contour tracing with feature extraction. The implementation is intended as a hardware accelerator in a self contained real-time digital surveillance system. The algorithm has lower memory requirements compared to other labeling techniques and can guarantee labeling of a predefined number of clusters independent of their shape. In addition, features especially important in this particular application are extracted during the contour tracing with little increase in hardware complexity. The implementation is verified on an FPGA in an embedded system environment with an image resolution of 320 times 240 at a frame rate of 25 fps. The implementation supports labeling of 61 independent clusters, extracting their location, size and center of gravity.

A complete MP3 decoder on a chip

The paper presents the results from a course project which focused on all levels in ASIC design flow by implementing a complete MP3 decoder. Two student teams developed a decoder targeting ASIC and FPGA, respectively. The ASIC decoder, fabricated in a 0.35 /spl mu/m process from AMI Semiconductor, consumes 40 mW with a supply voltage of 2 V running at 12 MHz. The FPGA decoder has been implemented and verified on a Virtex-II platform.

Teaching digital ASIC design to students with heterogeneous previous knowledge

This paper describes an MSc level digital ASIC project course. The majority of the course participants are international students, having a wide spread in previous knowledge in the field of digital HW-design. A course outline adapting to this fact has been developed, changing from one joint VLSI project towards smaller individual projects. The diversity in previous knowledge is evened out by adding lectures regarding design methodology and used EDA-tools, and making the first part of the course purely laboratory. To enhance and highlight different aspects of HDL-design, mandatory assignments allow the students to gradually take command over the complete design flow. As a result, comprehension of digital ASIC design is increased among the students and course administration is reduced.

Teaching digital HW-design by implementing a complete MP3 decoder

This paper describes a project course that focuses on all the different stages in an ASIC design flow. The project starts at algorithm level, followed by architecture selection, netlist generation, down to physical layout, fabrication, and finally verification. The scope of the project, implementing a complete MP3 decoder in VHDL and sending it for fabrication, motivates the students to work hard towards a common goal.

A manual on ASIC front to back end design flow

This paper presents a manual that covers the necessary design steps for a basic ASIC design flow. It is shown how the manual writing process is organized such that each chapter covers a certain step in the design flow. The manual has been written especially with practicality in mind and has been successfully applied to undergraduate and postgraduate teaching.

An architecture for calculation of the distance transform based on Mathematical Morphology

This paper presents a hardware architecture for calculating the city-block and chessboard distance transform on binary images. It is based on applying multiple morphological erosions and adding the result, enabling both processing pixels in raster scan order and a deterministic execution time. Which distance metric to be calculated is determined by the shape of the structuring element, i.e. diamonds for the city-block and squares for the chessboard. These properties together with a low memory requirement make the architecture applicable in any streaming data real-time embedded system environment with hard timing constraints, e.g. set by the frame rate. Depending on the application, a priori knowledge of the maximum size of the clusters may be used to reduce execution time and memory requirement even further. The architecture has been implemented for both FPGA and ASIC in an embedded system environment with an image resolution of 320 × 240 at a frame rate of 25 fps, running at 100 MHz and 454 MHz, respectively.